Page 1
H L 1 5 7 0 3
LCD Driver IC
HL15703
Preliminary
2Q. 1999
Hyundai Electronics Industries
System IC Division
1
P r e l i m i n a r y
Page 2
Contents
1. General Description
2. Features
3. Block Diagram
4. Pin Diagram
5. Pin Description
6. Serial I/O Data Format
7. Registers
HL15703
8. Key Scan Function
9. LCD Function
10. Power On Reset
11. Power Down Mode
12. Oscillator Port
13. Electrical Characteristics
14. Application
2
P r e l i m i n a r y
Page 3
HL15703
1. General Description
The HL15703 is 1/3 duty LCD display driver. It can drive directly maximum
171 segments. Also it has four general purpose output ports and a key scan
function that accepts input from up to 30 keys.
2. Features
• LCD display ..................................... 57 segments x 3 commons
1/3 duty - 1/2 bias
1/3 duty - 1/3 bias
• Key scan ............................................ Maximum 30 keys
Input 5 pins, Output 6 pins
• Power down mode ............................. Sleep mode and all segments off mode
• Port
Output .................................................. 4 pins
( Including the LCD segment port )
• Serial I/O .............................................. Data transfer and receive
• Power on reset ..................................... Supply voltage detection ( SVD )
• RC oscillator
• Package ............................................... 80QFP
Package Dimensions
80QFP
1.0
64
65
14.0
17.2
1.0
80
1.5
3.0 max
23.2
0.5
0.35
41
40
25
1 24
20.0
21.6
0.15
2.70
15.5
0.5
0.1
Unit : mm
3
P r e l i m i n a r y
Page 4
80QFP
14.0
12.0
61
1.25
0.5
1.25
60
1.25
0.20
14.0
12.0
0.5
1.25
41
HL15703
0.135
40
3. Block Diagram
VCL1
VCL2
VDD
VSS
RES
OSC
80
1
max
1.6
COM3
COM2
COM1
COMMOM
DRIVER
LCD
BIAS
SVD
CLOCK
GENERATOR
RESET
CLOCK
21
20
1.4
0.50.5
KS2 / SEG57
KS1 / SEG56
SEG55
SEGMENT
DRIVER
LCD
DISPLAY & CONTROL
REGISTER
SERIAL
I/O
0.1
Unit : mm
SEG5
SEG4 / P4
SEG1 / P1
SI
SO
SCK
CE
TEST
TEST
CONTROL
4
KS5
KS4
KS3
KS2
KEY
SCAN
KS1
KIN6
KIN5
KIN4
KIN3
KIN2
KIN1
P r e l i m i n a r y
Page 5
4. Pin Diagram
KS6
KS5
KS4
KS3
KS2 / S57
KS1 / S56
COM3
COM2
COM1
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
HL15703
S41
KI1
KI2
KI3
KI4
KI5
VDD
VDD1
VDD2
VSS
TEST
OSC
RES
DD
CE
CL
DI
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
KI5
VDD
VDD1
VDD2
VSS
TEST
OSC
RES
DD
CE
CL
DI
80
65
70
64
1
P1 / S1
P2 / S2
P3 / S3
KS2 / S57
61
70
80
1
60
S5S6S7S8S9
P4 / S4
KS1 / S56
COM3
COM2
COM1
50
10 20
S10
S11
S12
S13
S14
S15
S16
S17
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
5060
10 20
S18
S45
S19
S44
S20
S43
41
S21
S42
40
30
21
S22
S41
41
40
30
25
24
S23
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
P1 / S1
P2 / S2
P3 / S3
S5S6S7S8S9
P4 / S4
S10
5
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
P r e l i m i n a r y
Page 6
5. Pin Description
HL15703
PIN Name I/O
SEG[55:1] O
COM [3:1] O 3 LCD Common Pins
VCL[2:1] I 2 LCD Bias Pins
OSC I/O 1 Oscillator Input Pin
KS[6:1] O 6 Key Scan Output Pins
KIN[5:1] I 5 Key Scan Input Pins
CE I 1 Serial I/O Control Pin
SCK I 1 Serial I/O Clock Pin
SO O 1 Serial I/O Data Output Pin
SI I 1 Serial I/O Data Input Pin
TEST I 1 Test Pin. “1” Test mode , “0” Normal Mode
P[4:1] O 4 Output Port share SEG[4:1]
RES I 1 Reset Pin
VDD I
VSS
I
Pin Number
55
1
1 Ground Pin
LCD SEG Pins share P1,P2,P3 and P4
Power Supply Pin
Contents
6
P r e l i m i n a r y
Page 7
6. Serial I/O Data Format
1) Writing Mode
i )SCK is stopped at the low level
CE
SCK
HL15703
SI
SO
CE
SCK
SI
SO
B0 B1 B2 B3 A0 A1 A2 A3
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1 0 D1 D2 D3XX
Display data
D56
D57 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0
0
Control data DD
D113
0 1 0 0 0 0 1 0 D58 D59 D60XX
Display data
D114
0 0 0 0 0 1
0 0 0 0 0 0
Fixed data DD
0 0 0
CE
SCK
SI
SO
XX
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1 0 D115
D116 D117
Display data
D170
D171
0 0 0 0 1 0
0 0 0 0 0 0
Fixed data DD
7
0 0 0
P r e l i m i n a r y
Page 8
ii )SCK is stopped at the high level
CE
SCK
HL15703
SI
SO
CE
SCK
SI
SO
CE
SCK
SI
SO
B0 B1 B2 B3 A0 A1 A2 A3
B0 B1 B2 B3 A0 A1 A2 A3
XX
B0 B1 B2 B3 A0 A1 A2 A3
1 0 0 0 0 1 0 0 D2 D3XX
1 0 0 0 0 1 0 0 D59 D60XX
1 0 0 0 0 1 0 0
D1
D58
D115
Display data
Display data
D116 D117
Display data
D56
D57 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0
Control data DD
D113
D114
0 0 0 0 0
0 0 0 0
Fixed data DD
D170
D171
0 0 0 0 1
0 0 0 0
Fixed data DD
0 0 0 0
0 0 0 0
1
0
CCB address : 42H
D171~D1 : Display data
S0, S1 : Sleep control data
K0, K1 : Key scan output / Segment output selection data
P0, P1 : Segment output / general-purpose output port selection data
SC : Segment on / off control data
DR : 1/2 bias or 1/3 bias drive selection data
8
P r e l i m i n a r y
Page 9
2) Reading Mode
i ) SCK is stopped at the low level
CE
SCK
HL15703
SI
SO
ii ) SCK is stopped at the high level
CE
SCK
SI
SO
01000011XX XX
A3A1B3B1 A2A0B2B0
KD1 KD2 KD3 KD4 KD5 KD6 KD7 KD8 KD9 KD11
0
1000011XX XX
A3A1B3B1 A2A0B2B0
KD1 KD2 KD3 KD4 KD5 KD6 KD7 KD8 KD9 KD11
XX
KD10
KD12
Output data
KD29
KD30
XX
SAXX
X : don’ t care
Output data
KD10
K29
XXKD12
K30
SA
X : don’ t care
CCB : 43H
K30 ~ K1 : Key data
SA : Sleep acknowledge data
9
P r e l i m i n a r y
Page 10
7. Registers
1) Display Registers
Output Pin COM1 COM2 COM3
SEG1/P1 D1 D2 D3
SEG2/P2 D4 D5 D6
SEG3/P3 D7 D8 D9
SEG4/P4 D10 D11 D12
SEG5 D13 D14 D15
SEG6 D16 D17 D18
SEG7 D19 D20 D21
SEG8 D22 D23 D24
SEG9 D25 D26 D27
SEG10 D28 D29 D30
SEG11 D31 D32 D33
SEG12 D34 D35 D36
SEG13 D37 D38 D39
SEG14 D40 D41 D42
SEG15 D43 D44 D45
SEG16 D46 D47 D48
SEG17 D49 D50 D51
SEG18 D52 D53 D54
SEG19 D55 D56 D57
SEG20 D58 D59 D60
SEG21 D61 D62 D63
SEG22 D64 D65 D66
SEG23 D67 D68 D69
SEG24 D70 D71 D72
SEG25 D73 D74 D75
SEG26 D76 D77 D78
SEG27 D79 D80 D81
SEG28 D82 D83 D84
SEG29 D85 D86 D87
SEG30 D88 D89 D90
SEG31 D91 D92 D93
SEG32 D94 D95 D96
SEG33
SEG34
SEG36
SEG37
SEG38
SEG40
D97 D98 D99
D100 D101 D102
D103 D104 D105SEG35
D106 D107 D108
D109 D110 D111
D112 D113 D114
D115 D116 D117SEG39
D118 D119 D120
D121 D122 D123SEG41
D124 D125 D126SEG42
HL15703
10
P r e l i m i n a r y
Page 11
Output Pin COM1 COM2 COM3
SEG43 D127 D128 D129
SEG44 D130 D131 D132
SEG45 D133 D134 D135
SEG46 D136 D137 D138
SEG47 D139 D140 D141
SEG48 D142 D143 D144
SEG49 D145 D146 D147
SEG50 D148 D149 D150
SEG51 D151 D152 D153
SEG52 D154 D155 D156
SEG53 D157 D158 D159
SEG54 D160 D161 D162
SEG55 D163 D164 D165
KS1 / S56 D166 D167 D168
KS2 / S57 D169 D170 D171
HL15703
2) Control Registers
Bias Selection Register
DR
Bias Selection
0
1 1/2 Bias
1/3 Bias
Key Scan / Segment output Selection Register
Control Data
K0 K1
0 0
0 1
1 X
Output Pin Status
KS1/SEG56 KS2/SEG57
KS1 KS2
SEG56 KS2
SEG56 SEG57
Maximum number of Input Pins
Port Mode Register
Control Data
P0 P1
0 0
0 1
1 0
1 1
SEG1/ P1 SEG2/ P2
SEG1 SEG2
P1 P2
P1 P2
P1 P2 P3 P4
Output Pin Status
SEG3/ P3 SEG4/ P4
30
25
20
SEG3 SEG4
SEG3 SEG4
P3 SEG4
11
P r e l i m i n a r y
Page 12
Port Data Register
HL15703
Output Pin
SEG1 / P1
SEG2 / P2
SEG3 / P3
SEG4 / P4
Port Data Register
D1
D4
D7
D10
Sleep Mode Control Register
Control Data
S0 S1
0 0
0 1
1 0
1 1
Mode
Normal
Sleep
Sleep
Sleep
OSC
Oscillator
Operating
Stopped
Stopped
Stopped
SEG / COMMON
Display On/Off Control Register
Control Data
SC
0
1
Display Status
SEG1 ~ SEG57
On
Off
Output
Operating
L
L
L
Output Pin Status
KS1 KS2
H H
L L
L L
H H
KS3 KS4
H H
L L
L L
H H
KS5 KS6
H H
L H
H H
H H
Key Scan Data & Sleep Acknowledge Read
ADDRESS Read Data
K1 ~ K30, SA43H
KIN1 KIN1 KIN1 KIN1 KIN1
KS1 / SEG56
KS2 / SEG57
KS3
KS4
KS5
KS6
K1 K2 K3 K4 K5
K6 K7 K8 K9 K10
K11 K12 K13 K14 K15
K16 K17 K18 K19 K20
K21 K22 K23 K24 K25
K26 K27 K28 K29 K30
12
P r e l i m i n a r y
Page 13
HL15703
8. Key Scan Function
1) Key Scan Timing
The key scan period is 384T. The HL15703 scans the key twice and determines
that a key has been pressed when the key data agrees. It outputs a key data read
request 800T after starting a key scan. If the key data does not agree and a key
was pressed at that point, it scans the key again.Thus the HL15703 cannot detect
a key press shorter than 800T.
KS1
KS2
KS3
KS4
KS5
KS6
*)
1
*)
*)
*)
*)
*) *)
2
3
4
5
1
2
3
4
5
6
800T
Key on
*) In sleep mode the high / low state of these pins is determined by the S0,S1 bits in the control data.
Key scan output signals are not output from pins that are set low.
2) In normal mode
*)
*)
*)
*)
*)
6
• The pins KS1 to KS6 are set high.
• When a key is pressed a key scan is started and the keys are scanned until all
keys are released. Multiple key presses are recognized by determining whether
multiple key data bits are set.
• If a key is pressed for longer than 800T ( where T=1/fosc ) the HL15703
outputs a key data read request (a low level on SO pin) to the controller. The
controller acknowledges this request and reads the key data. However, if CE
is high during a serial data transfer, SO will be set high.
• After the controller reads the key data, the key data read requests is cleared (
SO pin is set high ) and the HL15703 performs another key scan. Also note
that SO pin, being an open-drain output, requires a pull-up resistor.
13
P r e l i m i n a r y
Page 14
Key input 1
Key input 2
Key Scan
CE
SI
SO
800T 800T 800T
Serial
data transfer
Serial
data transfer
Key
address
Key data read Key data read Key data read
Serial
data transfer
Key
address
HL15703
Key
address
Key data read request
Key data read request Key data read request
3) In sleep mode
• The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the
sleep mode control register.
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set
high is pressed, the oscillator on the OSC pin is started and a key scan is
performed. Keys are scanned until all keys are released. Multiple key pre sses are recognized by determining whether multiple key data bits are set.
• If a key is pressed for longer than 800T ( where T=1/fosc ) the HL15703
outputs a key data read request (a low level on SO) to the controller. The
controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, SO will be set high.
• After the controller reads the key data, the key data read request is cleared
( SO is set high ) and the HL15703 performs another key scan. However
this does not clear sleep mode. Also note that SO, being an open-drain
output, requires a pull-up resistor ( between 1 and 10 K).
• Sleep mode key scan example
Example : S0 = 0, S1 = 1 ( sleep with only KS6 high )
14
P r e l i m i n a r y
Page 15
HL15703
“L” KS1
“L” KS2
“L” KS3
When any one of these keys is pressed, the
oscillator on the OSC pin is started and the keys
are scanned.
“L” KS4
“L” KS5
“H” KS6
*)
KIN1
KIN2
KIN3
KIN4
KIN5
*) These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only
KS6 high, as in the above example. That is, these diodes prevent incorrect operation due to sneak currents in the KS6
key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
Key input
(KS6 line)
Key Scan
800T 800T
CE
Serial
data transfer
Serial
data transfer
Key
address
Serial
data transfer
Key
address
SI
SO
Key data read Key data read
Key data read request
Key data read request
Multiple Key Presses
Although the HL15703 is capable of key scanning without inserting diodes for
dual key presses, triple key presses on the KIN1 to KIN5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been
pressed. Therefore, a diode must be inserted in series with each key. Application
that do not recognize multiple key presses of threes or keys should check the key
data for three or more 1 bits and ignore such data.
15
P r e l i m i n a r y
Page 16
9. LCD Display Function
1) 1/3 Duty 1/2 Bias Waveforms
COM1
COM2
COM3
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are turned off.
HL15703
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
LCD driver output when all
LCD segments corresponding
to COM1 are on.
LCD driver output when all
LCD segments corresponding
to COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are on.
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
16
P r e l i m i n a r y
Page 17
2) 1/3 Duty 1/3 Bias Waveforms
COM1
COM2
COM3
HL15703
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are turned off.
LCD driver output when all
LCD segments corresponding
to COM1 are on.
LCD driver output when all
LCD segments corresponding
to COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM3 are on.
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
LCD driver output when all
LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are on.
17
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
P r e l i m i n a r y
Page 18
10. Power On Reset
1) Supply Voltage Detection ( SVD )
The SVD generates an output signal and resets the system when power is
first applied and when the voltage drops,I.,e when the power supply voltage is
less than or equal to the power down detection voltage, which is 2.5V, typical.
To assure that this function operates reliably, a capacitor must be added to the
power supply voltage Vdd rise time when power is first applied and the power
supply voltage Vdd fall time when the voltage drops are both at least 1ms.
2) System Reset
If at least 1ms is assured as the supply voltage Vdd rise time when power is
applied, a system reset will be applied by the SVD output signal when the supply
voltage is brought up. If at least 1ms is assured as the supply voltage Vdd fall
time when power drops, a system reset will be applied in the same manner by
the SVD output signal when the supply voltage is lowered.
HL15703
VDD
CE
Internal data
SVD
t1 t2
Display and control data transfer
Undefined
System reset period
Power supply voltage Vdd rise time : t1 > 1ms
Power supply voltage Vdd fall time : t2 > 1ms
Defined
SVD
3) Internal block states during the reset period
• Clock generator
Reset is applied and the base clock is stopped and OSC pin state is low.
• Common , segment drive and display data
Reset is applied and the display is turned off but display data is not cleared.
• Key scan
Reset is applied and all the key data is set to low.
18
P r e l i m i n a r y
Page 19
HL15703
4) Output pin states during the reset period
• SEG1/P1 to SEG4/P4 : Low *)
• SEG5 to SEG55 : Low
• COM1 to COM3 : Low
• KS1/SEG56, KS2/SEG57 : Low *)
• KS3 to KS5 : X
• KS6 : High
• SO : High
*) These output pins are forcibly set to the segment output function and held low.
11. Power Down Mode
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment
outputs will all go low and the common outputs will also go low, and the oscillator
on the OSC pin will stop ( it will be started by a key press). This reduces power
dissipation. This mode is cleared by sending control data with both S0 and S1 set
to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose
output ports according to the state of the P0 and P1 control data bits, even in
sleep mode.
19
P r e l i m i n a r y
Page 20
12. Oscillator Port
OSC Pin Diagram
OSC
HL15703
R
Internal clock
SLEEP
C
Oscillator circuit consists of internal R and C.
No Capacitor
OSC
Open
HL15703 has internal resistor and capacitor, so it can be oscillation without external capacitor.
If you want to adjust the clock period then you can adjust it using external capacitor.
Using Capacitor
OSC
C
20
P r e l i m i n a r y
Page 21
13. Electrical Characteristics
Absolute Maximum Rating at Ta=25¡É, Vss = 0V
HL15703
Parameter Symbol Condition
Maximum supply voltage VDD max VDD
Input voltage
Output voltage
Output current
Allowable power dissipation Pd max
Operating temperature Topr -40 to +85
Storage temperature Tstg -55 to +125
Vin1 CE,SCK,SI,RES -0.3 to +7.0 V
Vin2 OSC,KIN1 to KIN5, TEST,VCL1,2 -0.3 to VDD+0.3 V
Vout1 SO -0.3 to +7.0 V
Vout2
Iout1 SEG1 to SEG57 300 uA
Iout2 COM1 to COM3 3 mA
Iout3 KS1 to KS6 1 mA
Iout4 P1 to P4 5 mA
OSC, SEG1 to SEG57, COM1 to
COM3, KS1 to KS6, P1 to P4
Ta = 85¡É
Rating unit
-0.3 to +7.0 V
-0.3 to VDD+0.3 V
200 mW
Recommend operating ranges at Ta= -40¡É to +85¡É, Vss = 0V
Parameter Symbol Condition
Supply voltage VDD
Input voltage
Input high level voltage
Recommended external
capacitance
Guaranteed oscillation range KHz
Data setup time ns
Data hold time ns
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
SO output delay time
SO rise time
VCL1 V
VCL2 V
VIH1 V
VIH2
VILInput low level voltage
fOSC
tds
tdh
tcp
tcs
tch
t0H
toL
tr
tf
tdc
tdr
VDD
VCL1
VCL2
CE,SCK,SI,RES
KIN1 to KIN5
CE,SCK,SI,RES,KIN1 to KIN5
OSC
OSC
SCK,SI
SCK,SI
CE,SCK
CE,SCK
CE,SCK
SCK
SCK
CE,SCK,SI
CE,SCK,SI
SO,RPU = 4.7kΩ,
CL = 10pF*1
SO,RPU = 4.7kΩ,
CL = 10pF*1
min
4.5
0.8VDD
0.6VDD
19
160
160
160
160
160
160
160
typ
2/3VDD
1/3VDD
0
TBD
38
max
6.0
VDD
VDD
6.0
VDD
0.2VDD
76
¡É
¡É
unit
V
V
V
pFCOSC
ns
ns
ns
ns
ns
ns160
ns160
µs1.5
µs1.5
Note : *1.Since SO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and
load capacitance CL .
21
P r e l i m i n a r y
Page 22
Electrical Characteristics for the Allowable Operating Ranges
HL15703
Parameter Symbol Condition
Hysteresis VH
Supply voltage detection SVD V
IIH µAInput high level current
Input low level current
Pull-down resistance
Output off leakage current
Output high level voltage
Output low level voltage
Output middle level voltage*2
Oscillator frequency fOSC KHz45.630.4OSC : C = TBD
Current drain
IIL µA
VIFInput floating voltage
RPD
IOFFH
VOH1
VOH2
VOH3
VOH4
VOL1
VOL2
VOL3
VOL4
VOL5
VMID1
VMID2
VMID3
VMID4
VMID5
IDD1 µA100Sleep mode
IDD2 µA460
IDD3 µA400
CE,SCK,SI,RES,KIN5 to KIN5
CE,SCK,SI,RES : V1 = 6.0V
CE,SCK,SI RES: V1 = 0V
KIN1 to KIN5
KIN1 to KIN5 : VDD = 5.0V
SO : VO = 6.0V
KS1 to KS6 : I0 = -500µA
P1 to P4 : I0 = -1mA
SEG1 to SEG57 : I0 = -20µA
COM1 to COM3 : I0= -100µA
KS1 to KS6 : I0 = 25µA
P1 to P4 : I0 = 1mA
SEG1 to SEG57 : I0 = 20µA
COM1 to COM3 : I0 = 100µA
SO : I0 = 1 mA
COM to COM3 : 1/2 bias,
Io = ¡¾100µA
SEG1 to SEG57 : 1/3 bias,
Io = ¡¾20µA
SEG1 to SEG57 : 1/3 bias,
Io = ¡¾20µA
COM to COM3 : 1/3 bias,
Io = ¡¾100µA
COM to COM3 : 1/3 bias,
Io = ¡¾100µA
VDD = 6.0V, output open,
1/2 bias,fOSC = 38 KHz
VDD = 6.0V, output open,
1/3 bias,fOSC = 38 KHz
min
2.7
-5.0
50
VDD -1.2
VDD -1.0
VDD -1.0
VDD -1.0
0.2
1/2 VDD
-1.0
2/3VDD
-1.0
1/3VDD
-1.0
2/3VDD
-1.0
1/3VDD
-1.0
typ
O.1VDD
2.5
100
VDD -0.5
0.5
0.1
38
230
200
max
0.05VDD
250
VDD -0.2
1/2VDD
+1.0
2/3VDD
+1.0
1/3VDD
+1.0
2/3VDD
+1.0
1/3VDD
+1.0
3.3
5.0
6.0
1.5
1.0
1.0
unit
kΩ
µA
V
V
V
V
V
V
V
V
V
V1.0
V0.5
V
V
V
V
V
Note : *2. Excluding the bias voltage generation divider resistor built into VCL1 and VCL2
22
P r e l i m i n a r y
Page 23
Timing diagram of SIO
CE
HL15703
SCK
SI
SO
CE
t0H
tr tf
tds tdh
VIH1
t0L
VIL
SCK
SI
SO
tcp tcs
23
tdc
tch
tdr
P r e l i m i n a r y
Page 24
14. Application
LCD panel (up to 171 segments
1/2 bias ( for use with normal panels )
+5V
*1)
C ≥ 0.047uF
C
From the controller
To the controller
To the controller
power supply
*3)
VDD
VSS
TEST
VCL1
VCL2
RES
CE
SCK
SI
SO
*2)
K
I
N
5
OSC
K
I
N
4
HL15703
(p 1)
(general-purpose
output ports)
(p 2)
Used with the
(p 3)
backlight controller
(p 4)
or other circuit.
COM1
COM2
COM3
P1 / SEG1
P2 / SEG2
P3 / SEG3
P4 / SEG4
SEG5
.
.
.
.
.
SEG55
S
S
E
E
G
G
5
5
6
7
/
K
K
K
K
I
I
N
N
3
2
K
I
S
S
N
6
5
1
/
K
K
K
K
S
S
S
S
3
1
2
4
.
.
.
.
.
(SEG56)
(SEG57)
•
Key matrix
(up to 30 keys)
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the
HL15703 is reset by the SVD.
*2). If the RES pin is not used for system reset, it must be connected to VDD
*3). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
24
P r e l i m i n a r y
•
¡Æ
¡Æ
Page 25
LCD panel (up to 171 segments
1/3 bias ( for use with normal panels )
OSC
+5V
*1)
C ≥ 0.047uF
C C
VDD
VSS
TEST
VCL1
VCL2
COM1
COM2
COM3
P1 / SEG1
P2 / SEG2
P3 / SEG3
P4 / SEG4
SEG5
.
.
.
.
.
SEG55
.
.
.
.
.
HL15703
(p 1)
(general-purpose
output ports)
(p 2)
Used with the
(p 3)
backlight controller
(p 4)
or other circuit.
S
S
E
E
G
G
5
5
6
7
/
/
K
K
K
K
S
S
S
S
4
3
1
2
(SEG56)
(SEG57)
From the controller
To the controller
To the controller
power supply
*3)
RES
CE
SCK
SI
SO
*2)
K
I
N
5
K
K
K
K
K
I
I
I
N
N
N
4
3
2
K
I
S
S
N
6
5
1
•
Key matrix
(up to 30 keys)
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the
HL15703 is reset by the SVD.
*2). If the RES pin is not used for system reset, it must be connected to VDD
*3). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
•
¡Æ
¡Æ
25
P r e l i m i n a r y
Page 26
LCD panel (up to 171 segments
1/3 bias ( for use with large panels )
+5V
*1)
C ≥ 0.047uF
R
•
R
C
C
From the controller
To the controller
To the controller
power supply
•
R
*3)
VDD
VSS
TEST
VCL1
VCL2
RES
CE
SCK
SI
SO
*2)
K
I
N
5
OSC
K
I
N
4
HL15703
(p 1)
(general-purpose
output ports)
(p 2)
Used with the
(p 3)
backlight controller
(p 4)
or other circuit.
COM1
COM2
COM3
P1 / SEG1
P2 / SEG2
P3 / SEG3
P4 / SEG4
SEG5
.
.
.
.
.
SEG55
S
S
E
E
G
G
5
5
6
6
/
K
K
K
K
I
I
N
N
3
2
K
I
S
S
N
6
5
1
/
K
K
K
K
S
S
S
S
4
3
1
2
.
.
.
.
.
(SEG56)
(SEG57)
•
Key matrix
(up to 30 keys)
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the
HL15703 is reset by the SVD.
*2). If the RES pin is not used for system reset, it must be connected to VDD
*3). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
26
P r e l i m i n a r y
•
¡Æ
¡Æ
Loading...