Datasheet HL15604 Datasheet (HEI)

H L 1 5 6 0 4

LCD Driver IC

HL15604

Preliminary

2Q. 1999

Hyundai Electronics Industries

System IC Division

1

P r e l i m i n a r y

Contents

1. General Description

2. Features

3. Block Diagram

4. Pin Diagram

5. Pin Description

6. Serial I/O Data Format

7. Registers

HL15604

8. Key Scan Function

9. LCD Function

10. Power On Reset

11. Power Down Mode

12. Oscillator Port

13. Electrical Characteristics

14. Application

2

P r e l i m i n a r y

HL15604

1. General Description

The HL15604 is 1/3,1/4 duty LCD display driver. It can drive directly maximum 224 segments. Also it has four general purpose output ports and a key scan function that accepts input from up to 30 keys.

2. Features

• LCD display ..................................... 56 segments x 3 commons

1/3 duty - 1/2 bias 1/3 duty - 1/3 bias ………………………….. 56 segments x 4 commons 1/4 duty - 1/3 bias

• Key scan ............................................ Maximum 30 keys

Input 5 pins, Output 6 pins

• Power down mode ............................. Sleep mode and all segments off mode

• Port

Output .................................................. 4 pins

( Including the LCD segment port )

• Serial I/O .............................................. Data transfer and receive

• Power on reset ..................................... Supply voltage detection ( SVD )

• RC oscillator

• Package ............................................... 80QFP

Package Dimensions

80QFP

17.2

14.0

1.5

3.0 max

23.2

0.35

1.0

64

65

1.0

80

1 24

20.0

21.6

3

0.5

41 40

25

0.15

2.70

15.5

0.5

0.1

Unit : mm

P r e l i m i n a r y

80QFP

14.0

12.0

1.25

0.5

1.25

61

60

1.25

0.20

14.0

12.0

0.5

1.25

41

HL15604

0.135

40

3. Block Diagram

VCL1 VCL2

VDD

VSS

RES OSC

80

1

max

1.6

COM4

COM3

COM2

COMMOM

DRIVER

LCD BIAS

SVD

CLOCK

GENERATOR

COM1

RESET

CLOCK

21

20

1.4

0.50.5

KS2 / SEG56

KS1 / SEG55

SEG54

SEGMENT

DRIVER

LCD

DISPLAY & CONTROL

REGISTER

SERIAL

I/O

0.1

Unit : mm

SEG5

SEG4 / P4

SEG1 / P1

SI SO SCK CE

MODE

CONTROL

KS5

4

KS4

KS3

KS2

KEY

SCAN

KS1

KIN6

KIN5

KIN4

KIN3

KIN2

KIN1

P r e l i m i n a r y

4. Pin Diagram

KS6

KS5

KS4

KS3

KS2 / SEG56

KS1 / SEG55

COM4

COM3

COM2

COM1

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

HL15604

KIN1 KIN2 KIN3 KIN4 KIN5

VDD VCL1 VCL2

VSS

MODE

OSC

RES

SO CE

SCK

SI

64

65 70

80

1

P1 / SEG1

P2 / SEG2

60

SEG5

SEG6

SEG7

SEG8

P4 / SEG4

P3 / SEG3

KS2 / SEG56

KS1 / SEG55

COM4

COM3

COM2

50

10 20

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

COM1

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG18

SEG19

SEG20

SEG45

SEG44

SEG43

41

24

SEG21

SEG22

SEG23

SEG42

SEG41

40

30

25

SEG24

SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25

KS3 KS4 KS5

KS6 KIN1 KIN2 KIN3 KIN4 KIN5

VDD VCL1 VCL2

VSS

MODE

OSC

RES

SO CE

SCK

SI

61

70

80

1

P1 / SEG1

P2 / SEG2

SEG5

SEG6

SEG7

P4 / SEG4

P3 / SEG3

5060

10 20

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

5

41

40

30

21

SEG17

SEG18

SEG19

SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21

SEG20

P r e l i m i n a r y

5. Pin Description

HL15604

PIN Name I/O SEG[56:1] O COM [4:1] O 4 LCD Common Pins VCL[2:1] I 2 LCD Bias Pins OSC I/O 1 Oscillator Input Pin KS[6:1] O 6 Key Scan Output Pins KIN[5:1] I 5 Key Scan Input Pins CE I 1 Serial I/O Control Pin SCK I 1 Serial I/O Clock Pin SO O 1 Serial I/O Data Output Pin SI I 1 Serial I/O Data Input Pin P[4:1] O 4 Output Port share SEG[4:1] RES I 1 Reset Pin MODE I 1 3 Common, 4 Common Select Pin VDD I 1 Power Supply Pin VSS

I

Pin Number

56

1 Ground Pin

LCD SEG Pins share P1,P2,P3 and P4

Contents

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6. Serial I/O Data Format

1) 3Common Writing Mode

i )SCK is stopped at the low level

CE SCK

HL15604

SI SO

CE SCK SI SO

B0 B1 B2 B3 A0 A1 A2 A3

0 1 0 0 0 0 1 0 D1 D2 D3XX

Display data

D56

D57 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0

0

Control data DD

D111

0 1 0 0 0 0 1 0 D57 D58 D59XX

Display data

D114

0 0 0 0 0 1

0 0 0 0 0 0

Fixed data DD

0 0 0

CE SCK SI SO

XX

B0 B1 B2 B3 A0 A1 A2 A3

0 1 0 0 0 0 1 0 D115

D116 D117

Display data

D168

0

0 0 0 0 1 0

00

0 0 0 0 0 0

Fixed data DD

7

0 0 0

P r e l i m i n a r y

ii )SCK is stopped at the high level

CE SCK

HL15604

SI SO

CE SCK SI SO

B0 B1 B2 B3 A0 A1 A2 A3

XX

B0 B1 B2 B3 A0 A1 A2 A3

1 0 0 0 0 1 0 0 D2 D3XX

1 0 0 0 0 1 0 0 D59 D60XX

1 0 0 0 0 1 0 0

D1

D58

D115

Display data

D116 D117

Display data

D56

D57 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0

Control data DD

D113

D114

0 0 0 0 0

0 0 0 0

Fixed data DD

D168

0

00

0 0 0 0 1

0 0 0 0

Fixed data DD

0 0 0 0

1

0

Address : 42H D168~D1 : Display data S0, S1 : Sleep control data K0, K1 : Key scan output / Segment output selection data P0, P1 : Segment output / general-purpose output port selection data SC : Segment on / off control data DR : 1/2 bias or 1/3 bias drive selection data

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P r e l i m i n a r y

2) 4Common Writing Mode

i )SCK is stopped at the low level

CE SCK

HL15604

SI SO

CE SCK SI SO

B0 B1 B2 B3 A0 A1 A2 A3

0 1 0 0 0 0 1 0 D1 D2 D3XX

Display data

D75

D76 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0

0

Control data DD

D151

0 1 0 0 0 0 1 0 D77 D78 D79XX

Display data

D152

0 0 0 0 0 1

0 0 0 0 0 0

Fixed data DD

0 0 0

CE SCK SI SO

XX

B0 B1 B2 B3 A0 A1 A2 A3

0 1 0 0 0 0 1 0 D153

D154 D155

Display data

D224

0 0 0 0

9

0 0 0 0 1 0

0 0 0 0 0 0

Fixed data DD

0 0 0

P r e l i m i n a r y

ii )SCK is stopped at the high level

CE SCK

HL15604

SI SO

CE SCK SI SO

1 0 0 0 0 1 0 0 D2 D3XX

B0 B1 B2 B3 A0 A1 A2 A3

1 0 0 0 0 1 0 0 D78 D79XX

B0 B1 B2 B3 A0 A1 A2 A3

1 0 0 0 0 1 0 0XX

B0 B1 B2 B3 A0 A1 A2 A3

D1

D77

D153 D154

Display data

D155

D224

Display data

D75

D76 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0

Control data DD

D151

D152

0 0 0 0 0

0 0 0 0

Fixed data DD

0 0 0 0

0 0 0 0 1

0 0 0 0

Fixed data DD

0 0 0 0

1

0

Address : 42H D168~D1 : Display data S0, S1 : Sleep control data K0, K1 : Key scan output / Segment output selection data P0, P1 : Segment output / general-purpose output port selection data SC : Segment on / off control data DR : 1/2 bias or 1/3 bias drive selection data

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P r e l i m i n a r y

2) Reading Mode

i ) SCK is stopped at the low level

CE SCK

HL15604

SI SO

ii ) SCK is stopped at the high level

CE SCK SI SO

01000011XX XX

A3A1B3B1 A2A0B2B0

KD1 KD2 KD3 KD4 KD5 KD6 KD7 KD8 KD9 KD11

0

1000011XX XX

A3A1B3B1 A2A0B2B0

KD1 KD2 KD3 KD4 KD5 KD6 KD7 KD8 KD9 KD11

XX

KD10

KD12

Output data

KD29

KD30

XX

SAXX

X : don’ t care

Output data

KD10

K29

XXKD12

K30

SA

X : don’ t care

Address : 43H K30 ~ K1 : Key data SA : Sleep acknowledge data

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P r e l i m i n a r y

7. Registers

1) 1/3 Duty Display Registers

Output Pin COM1 COM2 COM3

SEG1/P1 D1 D2 D3 SEG2/P2 D4 D5 D6 SEG3/P3 D7 D8 D9 SEG4/P4 D10 D11 D12

SEG5 D13 D14 D15 SEG6 D16 D17 D18 SEG7 D19 D20 D21 SEG8 D22 D23 D24

SEG9 D25 D26 D27 SEG10 D28 D29 D30 SEG11 D31 D32 D33 SEG12 D34 D35 D36 SEG13 D37 D38 D39 SEG14 D40 D41 D42 SEG15 D43 D44 D45 SEG16 D46 D47 D48 SEG17 D49 D50 D51 SEG18 D52 D53 D54 SEG19 D55 D56 D57 SEG20 D58 D59 D60 SEG21 D61 D62 D63 SEG22 D64 D65 D66 SEG23 D67 D68 D69 SEG24 D70 D71 D72 SEG25 D73 D74 D75 SEG26 D76 D77 D78 SEG27 D79 D80 D81 SEG28 D82 D83 D84 SEG29 D85 D86 D87 SEG30 D88 D89 D90 SEG31 D91 D92 D93 SEG32 D94 D95 D96 SEG33 SEG34

SEG36 SEG37 SEG38

SEG40

D97 D98 D99 D100 D101 D102 D103 D104 D105SEG35 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117SEG39 D118 D119 D120 D121 D122 D123SEG41 D124 D125 D126SEG42

HL15604

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Output Pin COM1 COM2 COM3

SEG43 D127 D128 D129 SEG44 D130 D131 D132 SEG45 D133 D134 D135 SEG46 D136 D137 D138 SEG47 D139 D140 D141 SEG48 D142 D143 D144 SEG49 D145 D146 D147 SEG50 D148 D149 D150 SEG51 D151 D152 D153 SEG52 D154 D155 D156 SEG53 D157 D158 D159

SEG54 D160 D161 D162 KS1 / SEG55 D163 D164 D165 KS2 / SEG56 D166 D167 D168

HL15604

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P r e l i m i n a r y

2) 1/4 Duty Display Registers

HL15604

Output Pin COM1

SEG1/P1 D1 SEG2/P2 D5 SEG3/P3 D9 SEG4/P4 D13

SEG5 D17 SEG6 D21 SEG7 D25 SEG8 D29

SEG9 D33 SEG10 D37 SEG11 D41 SEG12 D45 SEG13 D49 SEG14 D53 SEG15 D57 SEG16 D61 SEG17 D65 SEG18 D69 SEG19 D73 SEG20 D77 SEG21 D81 SEG22 D85 SEG23 D89 SEG24 D93 SEG25 D97 SEG26 D101 SEG27 D105 SEG28 D109 SEG29 D113 SEG30 D117 SEG31 D121 SEG32 D125 SEG33 SEG34

SEG36 SEG37 SEG38

SEG40

D129 D133 D137 D141 D145 D149 D153 D157 D161 D165

COM2

D2

D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98

D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166

COM3

D3

D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99

D103 D107 D111 D115 D119 D123 D127 D131 D135 D139SEG35 D143 D147 D151 D155SEG39 D159 D163SEG41 D167SEG42

COM4

D4

D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96

D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168

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P r e l i m i n a r y

HL15604

Output Pin COM1 COM2 COM3

SEG43 D169 D170 D171 SEG44 D173 D174 D175 SEG45 D177 D178 D179 SEG46 D181 D182 D183 SEG47 D185 D186 D187 SEG48 D189 D190 D191 SEG49 D193 D194 D195 SEG50 D197 D198 D199 SEG51 D201 D202 D203 SEG52 D205 D206 D207 SEG53 D209 D210 D211

SEG54 D213 D214 D215 KS1 / SEG55 D217 D218 D219 KS2 / SEG56 D221 D222 D223

3) Control Registers

COM4

D172 D176 D180 D184 D188 D192 D196 D200 D204 D208 D212 D216 D220 D224

Bias Selection Register

DR

Bias Selection 0 1 1/2 Bias

1/3 Bias

Key Scan / Segment output Selection Register

Control Data

K0 K1

0 0 0 1 1 X

Output Pin Status

KS1/SEG55 KS2/SEG56

KS1 KS2 SEG55 KS2 SEG55 SEG56

Maximum number of Input Pins

Port Mode Register

Control Data

P0 P1

0 0 0 1 1 0 1 1

SEG1/ P1 SEG2/ P2

SEG1 SEG2

P1 P2 P1 P2 P1 P2 P3 P4

Output Pin Status

SEG3/ P3 SEG4/ P4

SEG3 SEG4 SEG3 SEG4

P3 SEG4

30 25 20

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P r e l i m i n a r y

Port Data Register

HL15604

Output Pin

SEG1 / P1 SEG2 / P2 SEG3 / P3 SEG4 / P4

Port Data Register

D1

D4

D7

D10

Sleep Mode Control Register

Control Data

S0 S1

0 0 0 1 1 0 1 1

Mode

Normal

Sleep Sleep Sleep

OSC

Oscillator

Operating

Stopped Stopped Stopped

SEG / COMMON

Display On/Off Control Register

Control Data

SC

0 1

Display Status

SEG1 ~ SEG56

On Off

Output

Operating

L L L

Output Pin Status

KS1 KS2

H H

L L L L

H H

KS3 KS4

H H L L L L H H

KS5 KS6

H H

L H H H H H

Key Scan Data & Sleep Acknowledge Read

ADDRESS Read Data

K1 ~ K30, SA43H

KIN1 KIN1 KIN1 KIN1 KIN1 KS1 / SEG55 KS2 / SEG56 KS3 KS4 KS5 KS6

K1 K2 K3 K4 K5

K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30

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P r e l i m i n a r y

HL15604

8. Key Scan Function

1) Key Scan Timing The key scan period is 384T. The HL15604 scans the key twice and determines

that a key has been pressed when the key data agrees. It outputs a key data read request 800T after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the key again.Thus the HL15604 cannot detect a key press shorter than 800T.

KS1

KS2

KS3

KS4

KS5

KS6

*)

1

*)

*) *)

2

3

4

5

1

2

3

4

5

6

800T

Key on

*) In sleep mode the high / low state of these pins is determined by the S0,S1 bits in the control data. Key scan output signals are not output from pins that are set low.

2) In normal mode

*)

6

• The pins KS1 to KS6 are set high.

• When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set.

• If a key is pressed for longer than 800T ( where T=1/fosc ) the HL15604 outputs a key data read request (a low level on SO pin) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high.

• After the controller reads the key data, the key data read requests is cleared ( SO pin is set high ) and the HL15604 performs another key scan. Also note that SO pin, being an open-drain output, requires a pull-up resistor.

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P r e l i m i n a r y

Key input 1

Key input 2

Key Scan

CE

SI

SO

800T 800T 800T

Serial data transfer

Key address

Serial data transfer

Key address

HL15604

Key address

Key data read Key data read Key data read

Key data read request

Key data read request Key data read request

3) In sleep mode

• The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the sleep mode control register.

• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key pre sses are recognized by determining whether multiple key data bits are set.

• If a key is pressed for longer than 800T ( where T=1/fosc ) the HL15604 outputs a key data read request (a low level on SO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high.

• After the controller reads the key data, the key data read request is cleared ( SO is set high ) and the HL15604 performs another key scan. However this does not clear sleep mode. Also note that SO, being an open-drain output, requires a pull-up resistor ( between 1 and 10 K).

• Sleep mode key scan example Example : S0 = 0, S1 = 1 ( sleep with only KS6 high )

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P r e l i m i n a r y

HL15604

“L” KS1 “L” KS2 “L” KS3

When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned.

“L” KS4 “L” KS5 “H” KS6

*)

KIN1 KIN2 KIN3 KIN4 KIN5

*) These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operation due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.

Key input (KS6 line)

Key Scan

800T 800T

CE

Serial data transfer

Key address

Serial data transfer

Key address

SI

SO

Key data read Key data read

Key data read request

Multiple Key Presses Although the HL15604 is capable of key scanning without inserting diodes for

dual key presses, triple key presses on the KIN1 to KIN5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Application that do not recognize multiple key presses of threes or keys should check the key data for three or more 1 bits and ignore such data.

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P r e l i m i n a r y

9. LCD Display Function

1) 1/3 Duty 1/2 Bias Waveforms ( MODE Pin = VSS )

COM1

COM2

COM3

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off.

HL15604

VDD VCL1,VCL2 0

LCD driver output when all LCD segments corresponding to COM1 are on.

LCD driver output when all LCD segments corresponding to COM2 are on.

LCD driver output when all LCD segments corresponding to COM1 and COM2 are on.

LCD driver output when all LCD segments corresponding to COM3 are on.

LCD driver output when all LCD segments corresponding to COM1 and COM3 are on.

LCD driver output when all LCD segments corresponding to COM2 and COM3 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

VDD VCL1,VCL2 0

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P r e l i m i n a r y

2) 1/3 Duty 1/3 Bias Waveforms ( MODE Pin = VSS )

COM1

COM2

COM3

HL15604

VDD VCL1 VCL2 0

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off.

LCD driver output when all LCD segments corresponding to COM1 are on.

LCD driver output when all LCD segments corresponding to COM2 are on.

LCD driver output when all LCD segments corresponding to COM1 and COM2 are on.

LCD driver output when all LCD segments corresponding to COM3 are on.

LCD driver output when all LCD segments corresponding to COM1 and COM3 are on.

VDD VCL1 VCL2 0

LCD driver output when all LCD segments corresponding to COM2 and COM3 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

21

VDD VCL1 VCL2 0

P r e l i m i n a r y

3) 1/4 Duty 1/3 Bias Waveforms ( MODE Pin = VDD )

COM1

COM2

COM3

COM4

LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are turned off.

LCD driver output when all LCD segments corresponding to COM1 are on.

LCD driver output when all LCD segments corresponding to COM2 are on.

LCD driver output when all LCD segments corresponding to COM1 and COM2 are on.

HL15604

VDD VCL1 VCL2 0

VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0

LCD driver output when all LCD segments corresponding to COM3 are on.

LCD driver output when all LCD segments corresponding to COM1 and COM3 are on.

LCD driver output when all LCD segments corresponding to COM2 and COM3 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

22

VDD VCL1 VCL2 0

P r e l i m i n a r y

COM1

COM2

COM3

COM4

HL15604

VDD VCL1 VCL2 0

LCD driver output when all LCD segments corresponding to COM4 are on.

LCD driver output when all LCD segments corresponding to COM1 and COM4 are on.

LCD driver output when all LCD segments corresponding to COM2 and COM4 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2 and COM4 are on.

LCD driver output when all LCD segments corresponding to COM3 and COM4 are on.

LCD driver output when all LCD segments corresponding to COM1, COM3 and COM4 are on.

LCD driver output when all LCD segments corresponding to COM2, COM3 and COM4 are on.

LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on.

VDD VCL1 VCL2 0 VDD VCL1 VCL2 0

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P r e l i m i n a r y

10. Power On Reset

1) Supply Voltage Detection ( SVD )

The SVD generates an output signal and resets the system when power is first applied and when the voltage drops,i.e., when the power supply voltage is less than or equal to the power down detection voltage, which is 2.5V, typical. To assure that this function operates reliably, a capacitor must be added to the power supply voltage VDD rise time when power is first applied and the power supply voltage VDD fall time when the voltage drops are both at least 1ms.

2) System Reset

If at least 1ms is assured as the supply voltage VDD rise time when power is applied, a system reset will be applied by the SVD output signal when the supply voltage is brought up. If at least 1ms is assured as the supply voltage VDD fall time when power drops, a system reset will be applied in the same manner by the SVD output signal when the supply voltage is lowered.

HL15604

VDD

CE

Internal data

SVD

t1 t2

Display and control data transfer

Undefined

System reset period

Power supply voltage VDD rise time : t1 > 1ms Power supply voltage VDD fall time : t2 > 1ms

Defined

SVD

3) Internal block states during the reset period

• Clock generator Reset is applied and the base clock is stopped and OSC pin state is low.

• Common , segment drive and display data Reset is applied and the display is turned off but display data is not cleared.

• Key scan Reset is applied and all the key data is set to low.

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P r e l i m i n a r y

HL15604

4) Output pin states during the reset period

• SEG1/P1 to SEG4/P4 : Low *)

• SEG5 to SEG54 : Low

• COM1 to COM4 : Low

• KS1/SEG55, KS2/SEG56 : Low *)

• KS3 to KS5 : X

• KS6 : High

• SO : High

*) These output pins are forcibly set to the segment output function and held low.

11. Power Down Mode

Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop ( it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose output ports according to the state of the P0 and P1 control data bits, even in sleep mode.

25

P r e l i m i n a r y

12. Oscillator Port

OSC Pin Diagram

OSC

HL15604

R

Internal clock

SLEEP

C

Oscillator circuit consists of internal R and C.

No Capacitor

OSC

Open

HL15604 has internal resistor and capacitor, so it can be oscillation without external capacitor. If you want to adjust the clock period then you can adjust it using external capacitor.

Using Capacitor

OSC

C

26

P r e l i m i n a r y

13. Electrical Characteristics

Absolute Maximum Rating at Ta=25¡É, Vss = 0V

HL15604

Parameter Symbol Condition

Maximum supply voltage VDD max VDD Input voltage

Output voltage

Output current

Allowable power dissipation Pd max Operating temperature Topr -40 to +85 Storage temperature Tstg -55 to +125

Vin1 CE,SCK,SI,RES -0.3 to +7.0 V Vin2 OSC,KIN1 to KIN5, TEST,VCL1,2 -0.3 to VDD+0.3 V

Vout1 SO -0.3 to +7.0 V Vout2

Iout1 SEG1 to SEG56 300 uA Iout2 COM1 to COM4 3 mA Iout3 KS1 to KS6 1 mA Iout4 P1 to P4 5 mA

OSC, SEG1 to SEG56, COM1 to COM4, KS1 to KS6, P1 to P4

Ta = 85¡É

Rating unit

-0.3 to +7.0 V

-0.3 to VDD+0.3 V

200 mW

Recommend operating ranges at Ta= -40¡É to +85¡É, Vss = 0V

Parameter Symbol Condition

Supply voltage VDD Input voltage

Input high level voltage

Recommended external capacitance

Guaranteed oscillation range KHz Data setup time ns Data hold time ns CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time

SO output delay time

SO rise time

VCL1 V VCL2 V

VIH1 V VIH2

VILInput low level voltage

fOSC

tds tdh tcp tcs tch

t0H

toL

tr

tf

tdc

tdr

VDD VCL1 VCL2 CE,SCK,SI,RES KIN1 to KIN5

CE,SCK,SI,RES,KIN1 to KIN5

OSC OSC

SCK,SI SCK,SI CE,SCK CE,SCK CE,SCK SCK SCK CE,SCK,SI CE,SCK,SI SO,RPU = 4.7kΩ,

CL = 10pF*1 SO,RPU = 4.7kΩ,

CL = 10pF*1

min

4.5

0.8VDD

0.6VDD

19 160 160 160 160 160 160 160

typ

2/3VDD 1/3VDD

0

TBD

38

max

6.0 VDD VDD

6.0 VDD

0.2VDD

76

¡É ¡É

unit

V

V V

pFCOSC

ns ns ns ns ns ns160 ns160

µs1.5

Note : *1.Since SO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and load capacitance CL .

27

P r e l i m i n a r y

Electrical Characteristics for the Allowable Operating Ranges

HL15604

Parameter Symbol Condition Hysteresis VH Supply voltage detection SVD V

IIH µAInput high level current

Input low level current

Pull-down resistance Output off leakage current

Output high level voltage

Output low level voltage

Output middle level voltage*2

Oscillator frequency f

Current drain

IIL µA

VIFInput floating voltage

RPD

IOFFH

VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5

VMID1

VMID2

VMID3

VMID4

VMID5

OSC

IDD1 µA100Sleep mode IDD2 µA460

IDD3 µA400

CE,SCK,SI,RES,KIN5 to KIN5

CE,SCK,SI,RES : VI = 6.0V CE,SCK,SI RES: VI = 0V KIN1 to KIN5 KIN1 to KIN5 : VDD = 5.0V SO : VO = 6.0V KS1 to KS6 : I0 = -500µA P1 to P4 : I0 = -1mA SEG1 to SEG56 : I0 = -20µA COM1 to COM4 : I0= -100µA KS1 to KS6 : I0 = 25µA P1 to P4 : I0 = 1mA SEG1 to SEG56 : I0 = 20µA COM1 to COM4 : I0 = 100µA SO : I0 = 1 mA COM to COM4 : 1/2 bias,

Io = ¡¾100µA SEG1 to SEG56 : 1/3 bias,

Io = ¡¾20µA SEG1 to SEG56 : 1/3 bias,

Io = ¡¾20µA COM to COM4 : 1/3 bias,

Io = ¡¾100µA COM to COM4 : 1/3 bias,

Io = ¡¾100µA

VDD = 6.0V, output open, 1/2 bias,fOSC = 38 KHz

VDD = 6.0V, output open, 1/3 bias,f

= 38 KHz

OSC

min

2.7

-5.0

50

VDD -1.2 VDD -1.0 VDD -1.0 VDD -1.0

0.2

1/2 VDD

-1.0

2/3VDD

-1.0

1/3VDD

-1.0

2/3VDD

-1.0

1/3VDD

-1.0

typ

O.1VDD

2.5

100

VDD -0.5

0.5

0.1

38

230

200

max

0.05VDD 250

VDD -0.2

1/2VDD

+1.0

2/3VDD

+1.0

1/3VDD

+1.0

2/3VDD

+1.0

1/3VDD

+1.0

3.3

5.0

6.0

1.5

1.0

unit

kΩ

µA

KHz45.630.4OSC : C = TBD

V

V V V V V V V V1.0 V0.5

V

Note : *2. Excluding the bias voltage generation divider resistor built into VCL1 and VCL2

28

P r e l i m i n a r y

Timing diagram of SIO

CE

HL15604

SCK

SI

SO

CE

t0H

tr tf

tds tdh

VIH1

t0L

VIL

SCK

SI

SO

tcp tcs

tdc

29

tch

tdr

P r e l i m i n a r y

14. Application

LCD panel (up to 168 segments)

1/2 bias ( for use with normal panels )

HL15604

(p 1)

(general-purpose output ports)

(p 2)

Used with the

(p 3)

backlight controller

(p 4)

or other circuit.

+5V

C ≥ 0.047uF

From the controller

To the controller To the controller

power supply

*3)

•

*1)

OSC

VDD

•

VSS

•

MODE

•

VCL1 VCL2

•

C

RES

*2)

CE SCK

K

SI SO

I

N

5

4

3

K

I

S

N

6

2

1

K

S

4

5

P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4

SEG54

K S 3

COM1 COM2 COM3

SEG5

.

S

E

G

5

6

/

K

S

1

2

*4)

•

.

(SEG55) (SEG56)

•

Key matrix (up to 30 keys)

Note : *1) Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL15604 is reset by the SVD. *2) If the RES pin is not used for system reset, it must be connected to VDD *3) The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *4) COM4 pin is no connection

30

P r e l i m i n a r y

•

¡Æ

LCD panel (up to 168 segments)

1/3 bias ( for use with normal panels )

HL15604

(p 1)

(general-purpose output ports)

(p 2)

Used with the

(p 3)

backlight controller

(p 4)

or other circuit.

+5V

C ≥ 0.047uF

From the controller

To the controller To the controller

power supply

C C

*3)

•

*1)

OSC

VDD

•

VSS

•

MODE

•

VCL1 VCL2

RES

*2)

CE SCK

K

SI SO

I

N

5

4

3

K

I

S

N

6

2

1

K

S

4

5

P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4

K S 3

*4)

COM1 COM2 COM3

SEG5

.

SEG54

S

E

G

5

6

/

K

S

1

2

•

.

(SEG55) (SEG56)

•

Key matrix (up to 30 keys)

Note : *1) Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL15604 is reset by the SVD. *2) If the RES pin is not used for system reset, it must be connected to VDD *3) The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *4) COM4 pin is no connection

31

P r e l i m i n a r y

•

¡Æ

LCD panel (up to 168 segments)

1/3 bias ( for use with large panels )

HL15604

(p 1)

(general-purpose output ports)

(p 2)

Used with the

(p 3)

backlight controller

(p 4)

or other circuit.

+5V

C ≥ 0.047uF

From the controller

To the controller To the controller

power supply

OSC

• •

*1)

R

•

R

C

•

R

•

*3)

VDD

VSS

•

MODE

•

VCL1 VCL2

RES

*2)

CE SCK

K

SI SO

I

N

5

4

3

K

I

S

N

6

2

1

K

S

4

5

P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4

COM2 COM3

SEG54

S E G 5 6 /

K

S

3

2

*4)

COM1

SEG5

.

S E G 5 5 / K S 1

•

.

(SEG55) (SEG56)

•

Key matrix (up to 30 keys)

Note : *1) Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL15604 is reset by the SVD. *2) If the RES pin is not used for system reset, it must be connected to VDD *3) The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *4) COM4 pin is no connection

32

P r e l i m i n a r y

•

¡Æ

LCD panel (up to 224 segments)

1/4 bias ( for use with large panels )

HL15604

(p 1)

(general-purpose output ports)

(p 2)

Used with the

(p 3)

backlight controller

(p 4)

or other circuit.

+5V

C ≥ 0.047uF

From the controller

To the controller To the controller

power supply

OSC

VDD

••

*1)

VSS

•

R

•

R

C

•

R

•

*3)

MODE

VCL1 VCL2

RES CE SCK

SI SO

*2)

K I N 5

K

I

N

4

3

2

K

I

S

N

6

5

1

COM1

COM2 COM3 COM4

P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4

SEG5

SEG54

S E G 5 6 /

K

S

4

3

2

•

.

S E G 5 5 / K S 1

.

(SEG55) (SEG56)

•

Key matrix (up to 30 keys)

Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL15604 is reset by the SVD. *2). If the RES pin is not used for system reset, it must be connected to VDD *3). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.

33

P r e l i m i n a r y

•

¡Æ