Page 1
H L 1 5 2 0 3
LCD Driver IC
HL15203
Preliminary
2Q. 1999
Hyundai Electronics Industries
System IC Division
1
P r e l i m i n a r y
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Contents
1. General Description
2. Features
3. Block Diagram
4. Pin Diagram
5. Pin Description
6. Serial I/O Data Format
7. Registers
HL15203
8. Key Scan Function
9. LCD Function
10. INH and Display Control
11. Power Down Mode
12. Oscillator Port
13. Electrical Characteristics
14. Application
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HL15203
1. General Description
The HL15203 is 1/3 duty LCD display driver. It can drive directly maximum
156 segments.
2. Features
• LCD display ..................................... 52 segments x 3 commons
1/3 duty - 1/2 bias
1/3 duty - 1/3 bias
• Power down mode ..........................…. Sleep mode and all segments off mode
• Serial I/O .............................................. Data transfer and receive
• RC oscillator
• Package ............................................... 64QFP
Package Dimensions
64QFP(14¡¿14)
1.6
49
1.0
14.0
17.2
Unit : mm
0.8
1.0
64
1
1.0
0.35
17.2
14.0
0.8
16
3348
32
17
1.0
2.70
1.6
0.15
64QFP(12¡¿12)
10.0
12.0
0.1
Unit : mm
48
49
64
12.0
10.0
1
0.35
16
0.5 1.25
1.7max
33
32
17
0.15
1.25
0.5
0.5
0.1
3
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3. Block Diagram
•
COM1
COM2
COM3
...........
SEG52
SEG51
HL15203
SEG1
VCL1
VCL2
INH
VDD
VSS
OSC
•
•
4. Pin Diagram
•
•
COMMON
DRIVER
•
LATCH & DRIVER
SHIFT REGISTER
•
CLOCK
GENERATOR
•
•
SI
SCK
ADDRESS
DETECTOR
CE
SEG49
SEG50
SEG51
SEG52
COM1
COM2
COM3
VDD
INH
VCL1
VCL2
VSS
OSC
CE
SCK
SI
49
64
48
1
SEG48
SEG47
SEG46
SEG2
SEG1
SEG3
SEG45
SEG44
SEG43
SEG42
SEG41
HL15203
SEG4
SEG5
SEG6
SEG7
SEG8
4
SEG40
SEG39
SEG38
SEG9
SEG10
SEG11
SEG37
SEG36
SEG35
SEG12
SEG13
SEG14
SEG34
SEG33
33
32
17
16
SEG15
SEG16
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
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5. Pin Description
PIN Name I/O Pin Number Contents
HL15203
SEG[52:1] O
COM [3:1] O 3 LCD Common Pins
VCL[2:1] I 2 LCD Bias Pins
OSC I 1 Oscillator Input Pin
CE I 1 Serial I/O Control Pin
SCK I 1 Serial I/O Clock Pin
SI I 1 Serial I/O Data Input Pin
INH I 1 Display off control pin
VDD I 1 Power Supply Pin
VSS I 1 Ground Pin
52
LCD SEG Pins
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DATA Writing
i ) SCK is stopped at the low level
CE
SCK
HL15203
SI
Address
8 bits
ii ) SCK is stopped at the high level
CE
SCK
SI
Address
8 bits
D2 D3
D1
01000011XX
A7A5A3A1 A6A4A2A0
Display data
156bits
D154 D155 D156
DR
BUSC
Control data
4 bits
¡¿
0
1000001XX
A7A5A3A1 A6A4A2A0
D2 D3
D1
Display data
156bits
D154 D155 D156
DR
BUSC
Control data
4 bits
¡¿
ADDRESS : 41H
D1 ~ D156 : Display data
Dn(n=1~156)=1 ……….. Display on
Dn(n=1~156)=0 ……….. Display off
DR : 1/2-bias drive or 1/3-bias drive switching control data
SC : Segments on/off control data
BU : Normal mode/power-saving mode control data
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DATA Writing Examples
i ) When 146 segments are used 146bits of display data (D11 to D156) must be sent.
CE
SCK
HL15203
SI
Address
8 bits
D12 D13
D11
01000011XX
A7A5A3A1 A6A4A2A0
Display data
146bits
D154 D155 D156
DR
Control data
ii ) When 122 segments are used 122bits of display data (D35 to D156) must be sent.
CE
SCK
SI
Address
8 bits
01000011XX
A7A5A3A1 A6A4A2A0
Display data
122bits
D36 D37
D35
iii ) When 37 segments are used 37bits of display data (D120 to D156) must be sent.
D154 D155 D156
DR
Control data
4 bits
4 bits
BUSC
¡¿
BUSC
¡¿
CE
SCK
SI
Address
8 bits
D121 D122
0
D120
1000001XX
A7A5A3A1 A6A4A2A0
Display data
37bits
7
D154 D155 D156
DR
BUSC
¡¿
Control data
4 bits
P r e l i m i n a r y
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7. Registers
1) Display Registers
Output Pin COM3 COM2 COM1
SEG1 D1 D2 D3
SEG2 D4 D5 D6
SEG3 D7 D8 D9
SEG4 D10 D11 D12
SEG5 D13 D14 D15
SEG6 D16 D17 D18
SEG7 D19 D20 D21
SEG8 D22 D23 D24
SEG9 D25 D26 D27
SEG10 D28 D29 D30
SEG11 D31 D32 D33
SEG12 D34 D35 D36
SEG13 D37 D38 D39
SEG14 D40 D41 D42
SEG15 D43 D44 D45
SEG16 D46 D47 D48
SEG17 D49 D50 D51
SEG18 D52 D53 D54
SEG19 D55 D56 D57
SEG20 D58 D59 D60
SEG21 D61 D62 D63
SEG22 D64 D65 D66
SEG23 D67 D68 D69
SEG24 D70 D71 D72
SEG25 D73 D74 D75
SEG26 D76 D77 D78
SEG27 D79 D80 D81
SEG28 D82 D83 D84
SEG29 D85 D86 D87
SEG30 D88 D89 D90
SEG31 D91 D92 D93
SEG32 D94 D95 D96
SEG33
SEG37
SEG38
SEG40
D97 D98 D99
D100 D101 D102SEG34
D103 D104 D105SEG35
D106 D107 D108SEG36
D109 D110 D111
D112 D113 D114
D115 D116 D117SEG39
D118 D119 D120
D121 D122 D123SEG41
D124 D125 D126SEG42
HL15203
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Output Pin COM3 COM2 COM1
SEG43 D127 D128 D129
SEG44 D130 D131 D132
SEG45 D133 D134 D135
SEG46 D136 D137 D138
SEG47 D139 D140 D141
SEG48 D142 D143 D144
SEG49 D145 D146 D147
SEG50 D148 D149 D150
SEG51 D151 D152 D153
SEG52 D154 D155 D156
2) Control Registers
HL15203
i) 1/2-bias drive or 1/3-bias drive switching control data
DR
Bias Selection
0
1 1/2 Bias
1/3 Bias
ii) Segments on/off control data
Control Data
SC
0
1
Display Status
SEG1 ~ SEG52
On
Off
iii) Normal mode/power-saving mode control data
BU
0
1
Normal Mode
Power-saving mode. In this mode the OSC pin oscillator is stopped
and the common and segment pins output Vss levels.
Mode
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9. LCD Display Function
1) 1/2 Bias, 1/3 Duty Waveforms
COM1
COM2
COM3
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are turned off.
HL15203
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
LCD driver output when all
LCD segments corresponding
to COM1 are on.
LCD driver output when all
LCD segments corresponding
to COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are on.
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
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2) 1/3 Duty 1/3 Bias Waveforms
COM1
COM2
COM3
HL15203
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are turned off.
LCD driver output when all
LCD segments corresponding
to COM1 are on.
LCD driver output when all
LCD segments corresponding
to COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM3 are on.
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
LCD driver output when all
LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are on.
11
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
P r e l i m i n a r y
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HL15203
10. INH and Display Control
Since the LSI internal data (D1 to D156, DR, SC, and BU) is undefined when
power is first applied, then display is off(SEG1 to SEG52,COM1 to COM3=low)
by setting the INH pin low at the same time as power is applied.Then meaningless
display at the power-on can be prevented by transferring serial data from the
controller while the display is off and setting INH pin high after the transfer completes.
VDD
INH
CE
••
R
•
C
t1
VIL
Transfer of display
and control data
VDD
INH
VIL
t2
Internal data
Undefined
t1 : Determined by the value of C and R
t2 : 10µs(minimum)
Defined
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HL15203
11. Power Down Mode
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment
outputs will all go low and the common outputs will also go low, and the oscillator
on the OSC pin will stop ( it will be started by a key press). This reduces power
dissipation. This mode is cleared by sending control data with both S0 and S1 set
to 0. Note that the SEG1 to SEG4 outputs can be used as general purpose output
ports according to the state of the P0 and P1 control data bits, even in sleep
mode.
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12. Oscillator Port
OSC Pin Diagram
OSC
HL15203
R
Internal clock
SLEEP
C
Oscillator circuit consists of internal R and C.
No Capacitor
OSC
Open
HL15203 has internal resistor and capacitor, so it can be oscillation without external capacitor.
If you want to adjust the clock period then you can adjust it using external capacitor.
Using Capacitor
OSC
C
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13. Electrical Characteristics
Absolute Maximum Rating at Ta=25¡É, Vss = 0V
HL15203
Parameter Symbol Condition
Maximum supply voltage VDD max VDD
Input voltage
Output voltage Vout OSC -0.3 to VDD+0.3 V
Output current
Allowable power dissipation Pd max
Operating temperature Topr -40 to +85
Storage temperature Tstg -55 to +125
Vin1 CE,SCK,SI,INH -0.3 to +6.5 V
Vin2 OSC -0.3 to VDD+0.3 V
Iout1 SEG1 to SEG52 300 uA
Iout2 COM1 to COM3 3 mA
Ta = 85¡É
Rating unit
-0.3 to +6.5 V
200 mW
Recommend operating ranges at Ta= -40¡É to +85¡É, Vss = 0V
Parameter Symbol Condition
Supply voltage VDD
Input voltage
Input high level voltage VIH V
Recommended external
capacitance
Guaranteed oscillation range KHz
Data setup time ns
Data hold time ns
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
INH switching time
VCL1 V
VCL2 V
VILInput low level voltage
f
OSC
tds
tdh
tcp
tcs
tch
t0h
tol
tr
tf
t2
VDD
VCL1
VCL2
CE,SCK,SI,INH
CE,SCK,SI,INH
OSC
OSC
SCK,SI
SCK,SI
CE,SCK
CE,SCK
CE,SCK
SCK
SCK
CE,SCK,SI
CE,SCK,SI
INH,CE
min
4.5
4.0
0
19
100
100
100
100
100
100
100
typ
2/3VDD
1/3VDD
TBD
38
max
6.0
6.0
6.0
6.0
0.7
76
¡É
¡É
unit
V
V
pFCOSC
ns
ns
ns
ns
ns
ns100
ns100
µs10
15
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Page 16
Electrical Characteristics for the Allowable Operating Ranges
HL15203
Parameter Symbol Condition
I
Input low level current
Oscillator frequency f
I
OSC
Hysteresis width VH
Output high level voltage
Output low level voltage
VOH1
VOH2
VOL1
VOL2
VMID1
VMID2
Intermediate level voltage*
VMID3
VMID4
VMID5
IDD1 µA5Power saving mode
IDD2 µA800f
Supply Current
IDD3 µA600f
IDD2 µA1300f
IDD3 µA1200f
5.0
1.0
1.0
unit
µAInput high level current
µA
kHzOSC : C = TBD
V
V
V
V
V
V
V
V
V
min
IH
IL
CE,SCK,SI,INH : V1 = 6.0V
CE,SCK,SI INH: V1 = 0V
-5.0
typ
max
38
CE,SCK,SI,INH,VDD=5V
SEG1 to SEG52 : IO = -20 µA
COM1 to COM3 : IO = -100 µA
0.3
VDD -1.0
VDD -1.0
SEG1 to SEG52 : IO = 20 µA V
COM1 to COM3 : IO = 100 µA
1/2 bias, COM1 to COM3:
Io = ¡¾100µA
1/3 bias, COM1 to COM3:
Io = ¡¾100µA
1/2 bias, COM1 to COM3:
Io = ¡¾100µA
1/3 bias ,SEG1 to SEG52 :
Io = ¡¾20µA
1/3 bias ,SEG1 to SEG52 :
Io = ¡¾20µA
= 38 kHz,1/2bias,VDD = 5V 400
OSC
= 38 kHz,1/3bias,VDD = 5V 300
OSC
= 38 kHz,1/2bias,VDD = 6V 650
OSC
= 38 kHz,1/3bias,VDD = 6V 580
OSC
1/2 VDD
±1.0
2/3VDD
± 1.0
1/3VDD
± 1.0
2/3VDD
± 1.0
1/3VDD
± 1.0
Note : *2. Except the bias voltage generation divider resistor that are built into VCL1 and VCL2
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Page 17
Timing diagram of SIO
CE
HL15203
SCK
SI
CE
SCK
VIH
VIL
t0h
tr tf
tds tdh
VIH
VIL
t0l
VIL
VIH
SI
tcp tcs
17
tch
P r e l i m i n a r y
Page 18
14. Application
LCD panel (up to 156 segments)
LCD panel (up to 156 segments)
1/3 bias ( for use with small panels )
VDD
VDD
INH
VSS
HL15203
OSC
COM1
COM2
COM3
OPEN
From the
microcontroller
VCL1
VCL2
CE
SCK
SI
1/3 bias ( for use with normal panels )
OSC
VDD
VDD
INH
VSS
SEG1
.
.
.
.
.
.
SEG52
COM1
COM2
COM3
C ≥ 0.047uF
From the
microcontroller
VCL1
C
C
VCL2
CE
SCK
SI
18
SEG1
.
.
.
.
.
.
SEG52
P r e l i m i n a r y
Page 19
1/3 bias ( for use with large panels )
LCD panel (up to 156 segments)
VDD
R
10 KΩ ≥ R ≥ 1 KΩ
C ≥ 0.047uF
From the
microcontroller
R
R
C
C
VDD
INH
VSS
VCL1
VCL2
CE
SCK
SI
OSC
COM1
COM2
COM3
SEG1
.
.
.
.
.
.
SEG52
HL15203
19
P r e l i m i n a r y
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