Datasheet HIP6601B, HIP6603B, HIP6604B Datasheet (intersil)

HIP6601B, HIP6603B, HIP6604B

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Data Sheet July 20, 2005

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FN9072.7

Synchronous Rectified Buck
MOSFET Drivers

The HIP6601B, HIP6603B and HIP6604B are high­frequency, dual MOSFET drivers specifically designed to
drive two power N-Channel MOSFETs in a synchronous
rectified buck converter topology. These drivers combined
with a HIP63xx or the ISL65xx series of Multi-Phase Buck
PWM controllers and MOSFETs form a complete core­voltage regulator solution for advanced microprocessors.

The HIP6601B drives the lower gate in a synchronous
rectifier to 12V, while the upper gate can be independently
driven over a range from 5V to 12V. The HIP6603B drives
both upper and lower gates over a range of 5V to 12V. This
drive-voltage flexibility provides the advantage of optimizing
applications involving trade-offs between switching losses
and conduction losses. The HIP6604B can be configured as
either a HIP6601B or a HIP6603B.

The output drivers in the HIP6601B, HIP6603B and
HIP6604B have the capacity to efficiently switch power
MOSFETs at frequencies up to 2MHz. Each driver is
capable of driving a 3000pF load with a 30ns propagation
delay and 50ns transition time. These products implement
bootstrapping on the upper gate with only an external
capacitor required. This reduces implementation complexity
and allows the use of higher performance, cost effective,
N-Channel MOSFETs. Adaptive shoot-through protection is
integrated to prevent both MOSF ETs fro m conducting
simultaneously.

Features

• Drives Two N-Channel MOSFETs

• Adaptive Shoot-Through Protection

• Internal Bootstrap Device

• Supports High Switching Frequency

- Fast Output Rise Time

- Propagation Delay 30ns

• Small 8 LD SOIC and EPSOIC and 16 LD QFN Packages

• Dual Gate-Drive Voltages for Optimal Efficiency

• Three-State Input for Output Stage Shutdown

• Supply Undervoltage Protection

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN—Quad Flat
No Leads—Product Outline.

- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile.

Applications

• Core Voltage Supplies for Intel Pentium® III, AMD®
Athlon™ Microprocessors

• High Frequency Low Profile DC-DC Converters

• High Current Low Voltage DC-DC Converters

Related Literature

• Technical Brief TB363, Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

TEMP. RANGE

PART NUMBER

(°C) PACKAGE

HIP6601BCB 0 to 85 8 Ld SOIC M8.15
HIP6601BCB-T 8 Ld SOIC Tape and Reel
HIP6601BECB 0 to 85 8 Ld EPSOIC M8.15B
HIP6601BECB-T 8 Ld EPSOIC Tape and Reel
HIP6603BCB 0 to 85 8 Ld SOIC M8.15
HIP6603BCB-T 8 Ld SOIC Tape and Reel
HIP6603BECB 0 to 85 8 Ld EPSOIC M8.15B
HIP6603BECB-T 8 Ld EPSOIC Tape and Reel
HIP6604BCR 0 to 85

16 Ld 4x4 QFN

HIP6604BCR-T 16 Ld 4x4 QFN Tape and Reel

PKG.

DWG. #

L16.4x4

Block Diagrams

HIP6601B AND HIP6603B

PVCC

VCC

+5V

SHOOT-

THROUGH

PROTECTION

PWM

10K

CONTROL

LOGIC

10K

Pinouts

†

HIP6601BCB, HIP6603BCB (SOIC)

HIP6601ECB, HIP6603ECB (EPSOIC)

TOP VIEW

UGATE

BOOT

PWM

GND

1
2
3
4

8
7
6
5

PHASE
PVCC
VCC
LGATE

HIP6604B (QFN)

TOP VIEW

NC

BOOT

PWM

GND

BOOT

UGATE

PHASE

LGATE

UGATENCPHASE

15

16 14 13

1

2

3

4

6578

NC

PGND

† VCC FOR HIP6601B

PVCC FOR HIP6603B

NC

12

11

10

9

NC

LGATE

NC

PVCC

LVCC

VCC

GND

PAD

FOR HIP6601ECB AND HIP6603ECB DEVICES, THE PAD ON THE BOTTOM
SIDE OF THE PACKAGE MUST BE SOLDERED TO THE PC BOARD.

HIP6604B QFN PACKAGE

2

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

Typical Application: 3-Channel Converter Using HIP6301 and HIP6601B Gate Drivers

+12V

+5V

BOOT

VCC

PWM

PVCC

DRIVE

HIP6601B

UGATE

PHASE

LGATE

+12V

PGOOD

VID

VFB

VSEN

FS

+5V

VCC

MAIN

CONTROL

HIP6301

GND

COMP

PWM1
PWM2
PWM3

ISEN1
ISEN2
ISEN3

VCC
PWM

VCC

PWM

+5V

PVCC

DRIVE

HIP6601B

+5V

PVCC

DRIVE

HIP6601B

BOOT

UGATE

PHASE

LGATE

BOOT

UGATE

PHASE

LGATE

+12V

+V

CORE

3

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

Absolute Maximum Ratings

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

BOOT Voltage (V
Input Voltage (V

UGATE. . . . . . .V

. . . . . . . . . . . .V

LGATE. . . . . . . . . GND - 5V(<400ns pulse width) to V

. . . . . . . . . . . . . . GND -0.3V(>400ns pulse width) to V

PHASE. . . . . . . . . . . . . . . . . . GND -5V(<400ns pulse width) to 15V

. . . . . . . . . . . . . . . . . . . . . . .GND -0.3V(>400ns pulse width) to 15V

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV

Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V

- V

BOOT

) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V

PWM

- 5V(<400ns pulse width) to V

PHASE

-0.3V(>400ns pulse width) to V

PHASE

) . . . . . . . . . . . . . . . . . . . . . . .15V

PHASE

BOOT
BOOT
PVCC
PVCC

+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

SOIC Package (Note 1) . . . . . . . . . . . . 97 N/A

EPSOIC Package (Note 2). . . . . . . . . . 38 N/A

QFN Package (Note 2). . . . . . . . . . . . . 48 10

Maximum Junction Temperature (Plastic Package) . . . . . . . .150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300°C

(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.

Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 85°C

Maximum Operating Junction Temperature . . . . . . . . . . . . . 125°C

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied .

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

2. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ

JA

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

JC,

the

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Bias Supply Current I

Upper Gate Bias Current I

VCC

PVCC

POWER-ON RESET

VCC Rising Threshold 9.7 9.95 10.4 V
VCC Falling Threshold 7.3 7.6 8.0 V

PWM INPUT

Input Current I

PWM

PWM Rising Threshold -3.6- V
PWM Falling Threshold -1.45- V
UGATE Rise Time t
LGATE Rise Time t
UGATE Fall Time t
LGATE Fall Time t
UGATE Turn-Off Propagation Delay t
LGATE Turn-Off Propagation Delay t

RUGATEVPVCC
RLGATEVPVCC
FUGATEVPVCC

FLGATEVPVCC
PDLUGATEVPVCC
PDLLGATEVPVCC

Shutdown Window 1.4 - 3.6 V
Shutdown Holdoff Time - 230 - ns

OUTPUT

Upper Drive Source Impedance R

Upper Drive Sink Impedance R

Lower Drive Source Current

Equivalent Drive Source Impedance
Lower Drive Sink Impedance R

UGATEVPVCC

UGATEVPVCC

I

LGATE

R

LGATE
LGATEVPVCC

HIP6601B, f
HIP6603B, f
HIP6601B, f
HIP6603B, f

V

= 0V or 5V (See Block Diagram) - 500 - µA

PWM

PWM
PWM
PWM
PWM

= 1MHz, V
= 1MHz, V
= 1MHz, V
= 1MHz, V

= 12V - 4.4 6.2 mA

PVCC

= 12V - 2.5 3.6 mA

PVCC

= 12V - 200 430 µA

PVCC

= 12V - 1.8 3.3 mA

PVCC

= 12V, 3nF Load - 20 - ns
= 12V, 3nF Load - 50 - ns
= 12V, 3nF Load - 20 - ns
= 12V, 3nF Load - 20 - ns
= 12V, 3nF Load - 30 - ns
= 12V, 3nF Load - 20 - ns

= 5V - 1.7 3.0 Ω

V

= 12V - 3.0 5.0 Ω

PVCC

= 5V - 2.3 4.0 Ω

V

= 12V - 1.1 2.0 Ω

PVCC

V

= 5V 400 580 - mA

PVCC

= 12V 500 730 - mA

V

PVCC

V

= 5V - 9 - Ω

PVCC

= 5V or 12V - 1.6 4.0 Ω

4

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

Functional Pin Description

UGATE (Pin 1), (Pin 16 QFN)

Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.

BOOT (Pin 2), (Pin 2 QFN)

Floating bootstrap supply pin for the upper gate drive.
Connect a bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. A resistor in series with boot
capacitor is required in certain applications to reduce ringing
on the BOOT pin. See the Internal Bootstrap Device section
under DESCRIPTION for guidance in choosing the
appropriate capacitor and resistor values.

PWM (Pin 3), (Pin 3 QFN)

The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.

GND (Pin 4), (Pin 4 QFN)

Bias and reference ground. All signals are referenced to
this node.

PGND (Pin 5 QFN Package Only)

This pin is the power ground return for the lower gate driver.

LGATE (Pin 5), (Pin 7 QFN)

Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.

VCC (Pin 6), (Pin 9 QFN)

Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND.

LVCC (Pin 10 QFN Package Only)

Lower gate driver supply voltage.

PVCC (Pin 7), (Pin 11 QFN)

For the HIP6601B and the HIP6604B, this pin supplies the
upper gate drive bias. Connect this pin from +12V down to +5V.

For the HIP6603B, this pin supplies both the upper and
lower gate drive bias. Connect this pin to either +12V or +5V.

PHASE (Pin 8), (Pin 14 QFN)

Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. The PHASE voltage is
monitored for adaptive shoot-through protection. This pin
also provides a return path for the upper gate drive.

Description

Operation

Designed for versatility and speed, the HIP6601B, HIP6603B
and HIP6604B dual MOSFET drivers control both high-side
and low-side N-Channel FETs from one externally provided
PWM signal.

The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [t
lower gate begins to fall. Typical fall times [t

PDLLGATE

FLGATE

provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [t

PDHUGATE

on how quickly the LGATE voltage drops below 2.2V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[t

RUGATE

] and the upper MOSFET turns on.

], the

] are

] based

Timing Diagram

PWM

UGATE

LGATE

t

PDLLGATE

t

PDHUGATE

t

FLGATE

5

t

RUGATE

t

PDLUGATE

t

FUGATE

t

PDHLGATE

t

RLGATE

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t

PDLUGATE

upper gate begins to fall [t

] is encountered before the

FUGATE

]. Again, the adaptive
shoot-through circuitry determines the lower gate delay time,
t

PDHLGATE

. The PHASE voltage is monitored and the lower
gate is allowed to rise after PHASE drops below 0.5V. The
lower gate then rises [t

RLGATE

], turning on the lower

MOSFET.

Three-State PWM Input

A unique feature of the HIP660X drivers is the addition of a
shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the Electrical Specifications determine
when the lower and upper gates are enabled.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.

During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 2.2V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 0.5V, the LGATE
is allowed to rise. PHASE continues to be monitored during
the lower gate rise time. If PHASE has not dropped below

0.5V within 250ns, LGATE is taken high to keep the
bootstrap capacitor charged. If the PHASE voltage exceeds
the 0.5V threshold during this period and remains high for
longer than 2µs, the LGATE transitions low. Both upper and
lower gates are then held low until the next rising edge of the
PWM signal.

Power-On Reset (POR) Function

During initial start-up, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.95V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of

7.6V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.

Internal Bootstrap Device

The HIP6601B, HIP6603B, and HIP6604B drivers all feature
an internal bootstrap device. Simply adding an external
capacitor across the BOOT and PHASE pins completes the
bootstrap circuit.

The bootstrap capacitor must have a maximum voltage
rating above VCC + 5V. The bootstrap capacitor can be
chosen from the following equation:

Q

GATE

BOOT

------------------------

≥

∆V

BOOT

is the amount of gate charge required to fully

GATE

BOOT

term is

C

Where Q
charge the gate of the upper MOSFET. The ∆V
defined as the allowable droop in the rail of the upper drive.

As an example, suppose a HUF76139 is chosen as the
upper MOSFET. The gate charge, Q

, from the data

GATE

sheet is 65nC for a 10V upper gate drive. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.325µF is required.
The next larger standard value capacitance is 0.33µF.

In applications which require down conversion from +12V or
higher and PVCC is connected to a +12V source, a boot
resistor in series with the boot capacitor is required. The
increased power density of these designs tend to lead to
increased ringing on the BOOT and PHASE nodes, due to
faster switching of larger currents across given circuit
parasitic elements. The addition of the boot resistor allows
for tuning of the circuit until the peak ringing on BOOT is
below 29V from BOOT to GND and 17V from BOOT to VCC.
A boot resistor value of 5Ω typically meets this criteria.

In some applications, a well tuned boot resistor reduces the
ringing on the BOOT pin, but the PHASE to GND peak
ringing exceeds 17V. A gate resistor placed in the UGATE
trace between the controller and upper MOSFET gate is
recommended to reduce the ringing on the PHASE node by
slowing down the upper MOSFET turn-on. A gate resistor
value between 2Ω to 10Ω typically reduces the PHASE to
GND peak ringing below 17V.

Gate Drive Voltage Versatility

The HIP6601B and HIP6603B provide the user total
flexibility in choosing the gate drive voltage. The HIP6601B
lower gate drive is fixed to VCC [+12V], but the upper drive
rail can range from 12V down to 5V depending on what
voltage is applied to PVCC. The HIP6603B ties the upper
and lower drive rails together. Simply applying a voltage
from 5V up to 12V on PVCC will set both driver rail voltages.

Power Dissipation

Package power dissipation is mainly a fu nct i on of th e
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation

6

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:

3



P1.05f

where f
and V
and Q

-- -

QUVLQ



2

is the switching frequency of the PWM signal. VU

sw

represent the upper and lower gate rail voltage. QU

L

is the upper and lower gate charge determined by

L

L

+

V

sw

U

I

DDQ

VCC+=

MOSFET selection and any external capacitance added to
the gate pins. The I

DDQ VCC

product is the quiescent power

of the driver and is typically 30mW.
The power dissipation approximation is a result of power

transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.

The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the MOSFET.

P

REFRESH

where Q

1

-- -

Q

==

f

SW

2

is the total charge removed from the bootstrap

LOSS

LOSS

V

PVCC

1

-- -

QUV

f

SW

2

U

capacitor and provided to the upper gate load.
The 1.05 factor is a correction factor derived from the

following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. C

and CL are the upper and lower gate load

U

capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value is

0.01µF.

Test Circuit

+5V OR +12V

+12V

0.15µF

0.15µF

1000

CU = CL = 3nF

800

600

400

POWER (mW)

200

0 500 1000 1500 2000

FIGURE 1. POWER DISSIPATION vs FREQUENCY

1000

VCC = PVCC = 12V

800

600

400

POWER (mW)

200

+5V OR +12V

PVCC

VCC

PWM

CU = CL = 4nF
C

U

CU = CL = 3nF

0.01µF

BOOT

UGATE

HIP660X

PHASE

LGATE

2N7002

C

GND

= CL = 5nF

FREQUENCY (kHz)

L

VCC = PVCC = 12V

CU = 3nF

C

CU = 0nF

C

= 3nF

L

CU = CL = 1nF

2N7002

CU = CL = 2nF

= 0nF

L

100kΩ

C

U

In Figure 1, C

and CL values are the same and frequency

U

is varied from 50kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply. Curves do exceed the 800mW
cutoff, but continuous operation above this point is not
recommended.

Figure 2 shows the dissipation in the driver with 3nF loading
on both gates and each individually. Note the higher upper
gate power dissipation which is due to the bootstrap device
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply.

7

0 500 1000 1500 2000

FREQUENCY (kHz)

FIGURE 2. 3nF LOADING PROFILE

The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate capacitors
are varied from 1nF to 5nF. VCC and PVCC are tied together
and to a +12V supply. Figures 4, 5 and 6 show the same
characterization for the HIP6603B with a +5V supply on PVCC
and VCC tied to a +12V supply.

Since both upper and lower gate capacitance can vary,
Figure 8 shows dissipation curves versus lower gate
capacitance with upper gate capacitance held constant at three
different values. These curves apply only to the HIP6601B due
to power supply configuration.

FN9072.7

July 20, 2005

Typical Performance Curves

1000

VCC = PVCC = 12V
FREQUENCY

800

600

400

POWER (mW)

200

0

1.0 2.0 3.0 4.0 5.0

FIGURE 3. POWER DISSIPATION vs LOADING

= 1MHz

FREQUENCY = 500kHz

FREQUENCY = 200kHz

GATE CAPACITANCE (CU = CL) (nF)

HIP6601B, HIP6603B, HIP6604B

400

VCC = 12V, PVCC = 5V

300

CU = CL = 5nF

CU = CL = 4nF

200

CU = CL = 3nF

POWER (mW)

100

0

0 500 1000 1500 2000

FIGURE 4. POWER DISSIPATION vs FREQUENCY (HIP6603B)

CU = CL = 2nF

CU = CL = 1nF

FREQUENCY (kHz)

400

VCC = 12V, PVCC = 5V

300

CU = CL = 3nF

200

CU = 3nF
C

= 0nF

POWER (mW)

100

0

L

CU = 0nF
C

= 3nF

L

0 500 1000 1500 2000

FREQUENCY (kHz)

400

VCC = 12V,

300

200

POWER (mW)

100

0

1.0 2.0 3.0 4.0 5.0

FREQUENCY = 1MHz

FREQUENCY = 500kHz

FREQUENCY = 500kHz

FREQUENCY = 200kHz

GATE CAPACITANCE = (C

= CL) (nF)

U

FIGURE 5. 3nF LOADING PROFILE (HIP6603B) FIGURE 6. VARIABLE LOADING PROFILE (HIP6603B)

1000

VCC = 12V, PVCC = 5V

800

FREQUENCY = 1MHz

600

500

VCC = 12V, PVCC = 5V

FREQUENCY = 500kHz

400

300

C

C

= 5nF

U

= 3nF

U

PVCC = 5V

400

POWER (mW)

200

0

1.0 2.0 3.0 4.0 5.0
GATE CAPACITANCE (C

FREQUENCY = 500kHz

FREQUENCY = 200kHz

= CL) (nF)

U

FIGURE 7. POWER DISSIPATION vs FREQUENCY (HIP6601B)

8

200

POWER (mW)

100

1.02.03.04.05.0
LOWER GATE CAPACITANCE (CL) (nF)

C

= 1nF

U

FIGURE 8. POWER DISSIPATION vs LOWER GATE

CAPACITANCE FOR FIXED VALUES OF UPPER
GATE CAPACITANCE

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

Small Outline Exposed Pad Plastic Packages (EPSOIC)

N

INDEX
AREA

123

TOP VIEW

-A­D

e

B

0.25(0.010) C AM BS

SIDE VIEW

123

N

P

BOTTOM VIEW

H

E

-B-

SEATING PLANE

A

-C-

A1

M

P1

0.25(0.010) BM M

L

h x 45

α

0.10(0.004)

M8.15B

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.056 0.066 1.43 1.68 -

A1 0.001 0.005 0.03 0.13 -

B 0.0138 0.0192 0.35 0.49 9

C 0.0075 0.0098 0.19 0.25 -

D 0.189 0.196 4.80 4.98 3

E 0.150 0.157 3.31 3.39 4

o

e 0.050 BSC 1.27 BSC -

H 0.230 0.244 5.84 6.20 -

h 0.010 0.016 0.25 0.41 5

L 0.016 0.035 0.41 0.64 6

C

N8 87

α

0° 8° 0° 8° -

P - 0.094 - 2.387 11

P1 - 0.094 - 2.387 11

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.

NOTESMIN MAX MIN MAX

Rev. 3 6/05

9

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A2 - - 1.00 9
A3 0.20 REF 9

b 0.23 0.28 0.35 5, 8

D 4.00 BSC ­D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8

E 4.00 BSC ­E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8

e 0.65 BSC -

k0.25 - - -

L 0.50 0.60 0.75 8
L1 - - 0.15 10

N162
Nd 4 3
Ne 4 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 5 5/04

10

FN9072.7

July 20, 2005

HIP6601B, HIP6603B, HIP6604B

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6
N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

11

FN9072.7

July 20, 2005