Datasheet HIP6021 Datasheet (Intersil Corporation)

HIP6021

Data Sheet February 1999 File Number

Advanced PWM and Triple Linear Power
Controller

The HIP6021 provides the power control and protection for
four output voltages in high-performance, graphics intensive
microprocessor and computer applications. The IC
integrates a voltage-mode PWM controller and three linear
controllers, as well as the monitoring and protection
functions into a 28-pin SOIC package. The PWM controller
regulates the microprocessor core voltage with a
synchronous-rectified buck converter. The linear controllers
regulate the computer system’s AGP 1.5V or 3.3V bus
power, the 1.5V GTL bus power, and the 1.8V power for the
North/South Bridge core voltage and/or cache memory
circuits. The HIP6021 includes an Intel-compatible, TTL
5-input digital-to-analog converter (DAC) that adjusts the
core PWM output voltage from 1.3V
steps and from 2.1V

to 3.5VDC in 0.1V increments. The

DC

to 2.05VDC in 0.05V

DC

precision reference and voltage-mode control provide±1%
static regulation. The AGP bus power linear controller’s
output (V

) isuser-selectable, throughaTTL-compatible

OUT2

signal applied at the SELECT pin, for levels of 1.5V or 3.3V
with ±3% accuracy. Based on the status of the FIX pin, the
other two linear regulators provide either fixed output
voltages of 1.5V±3% (V

) and 1.8V±3% (V

OUT3

OUT4

), or
user-adjustable by means of an external resistor divider. All
linear controllers can employ either N-channel MOSFETs or
bipolar NPNs for the pass transistor.

The HIP6021 monitors all the output voltages. A single
Power Good signal isissuedwhenthe core is within ±10% of
the DAC setting and all other outputs are above their under­voltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
controller’s over-currentfunction monitors the output current
by using the voltage drop across the upper MOSFET’s
r

DS(ON)

.

Ordering Information

TEMP.

PART NUMBER

HIP6021CB 0 to 70 28 Ld SOIC M28.3
HIP6021EVAL1 Evaluation Board

RANGE (oC) PACKAGE

PKG.

NO.

Applications

•

Motherboard Power Regulation for Computers

4684

Features

• Provides 4 Regulated Voltages

- Microprocessor Core, AGP Bus, Memory, and GTL Bus
Power

• Drives N-Channel MOSFETs

• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors

• Fixed or Externally Resistor-Adjustable Linear Outputs
(FIX Pin)

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulation

- Core PWM Output: ±1% Over Temperature

- Other Outputs: ±3% Over Temperature

• TTL-Compatible 5-Bit DAC Microprocessor Core Output
Voltage Selection

- Wide Range . . . . . . . . . . . . . . . . . . . 1.3V

DC

to 3.5V

• Power-Good Output Voltage Monitor

• Over-Voltage and Over-Current Fault Monitors

- Switching Regulator Does Not Require Extra Current

Sensing Element, Uses MOSFET’s r

DS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator; Programmable From

50kHz to Over 1MHz

- Small External Component Count

Pinout

HIP6021 (SOIC)

TOP VIEW

VCC

DRIVE2

FIX
VID4
VID3
VID2
VID1
VID0

PGOOD

SD

VSEN2

SELECT

SS

FAULT/RT

VSEN4

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

UGATE
PHASE
LGATE
PGND
OCSET
VSEN1
FB
COMP
VSEN3
DRIVE3
GND
VAUX
DRIVE4

DC

2-296

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

Block Diagram

HIP6021

VCC

OCSET

VSEN1

SD

FIX

VAUX

POWER-ON

RESET (POR)

200µA

+

x 1.10

PGOOD

VCC

-

+

x 0.90

-

LUV

-

+

x 1.15

LINEAR

UNDER-

OV

VOLTAGE

UGATE

DRIVE1

SOFT-

START

INHIBIT

+

OC1

LOGIC

AND FAULT

FAULT

PHASE

-

GATE

LGATE

VCC

CONTROL

PWM1

PWM

COMP1

-

+

-

+

AMP1

ERROR

PGND

DRIVE

SYNCH

VCC

GND

TTL D/A

CONVERTER

DACOUT

28µA

VID4

VID3

(DAC)

4.5V

VID2

VID1

VID0

COMP

FB

SS

VSEN3

VAUX

2-297

-

-

+

DRIVE3

+

x 0.75

+

DRIVE4

-

+

1.26V

-

+

+

-

+

-

VSEN4

-

DRIVE2

VSEN2

x 0.75

OSCILLATOR

or

3.3V

1.5V

-

+

SELECT

FAULT / RT

Simplified Power System Diagram

+5V

IN

+3.3V

IN

Q3

V

OUT2

HIP6021

LINEAR

CONTROLLER

HIP6021

PWM

CONTROLLER

Q1

Q2

V

OUT1

V

Typical Application

+12V

IN

+5V

IN

+3.3V

IN

V

OUT2

1.5V OR 3.3V

TYPEDET

V

OUT3

1.5V

L

IN

OUT3

Q4

C

IN

Q4

C

Q3

OUT2

DRIVE2

VSEN2

SELECT

VAUX

DRIVE3

VSEN3

LINEAR

CONTROLLER

HIP6021

VCC

LINEAR

CONTROLLER

OCSET

PGOOD

UGATE
PHASE

LGATE
PGND

VSEN1

FB

COMP

Q1

Q2

Q5

L

OUT1

C

OUT1

V

OUT4

POWERGOOD

1.3V TO 3.5V

V

OUT1

V

1.8V

OUT4

C

C

OUT3

OUT4

Q5

2-298

FIX

DRIVE4

VSEN4

SS

C

SS

GND

FAULT / RT

VID0
VID1
VID2

VID3
VID4

HIP6021

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

PGOOD, RT/FAULT, DRIVE, PHASE,

and GATE Voltage . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V

Input, Output or I/O Voltage. . . . . . . . . . . . . . . . . . GND -0.3V to 7V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply Current I

CC

POWER-ON RESET

Rising VCC Threshold V
Falling VCC Threshold V
Rising VAUX Threshold V
VAUX Threshold Hysteresis V
Rising V

Threshold - 1.26 - V

OCSET

OSCILLATOR

Free Running Frequency F

OSC

Total Variation 6kΩ < RT to GND < 200kΩ -15 - +15 %
Ramp Amplitude ∆V

OSC

DAC AND BANDGAP REFERENCE

DAC(VID0-VID4) Input Low Voltage - - 0.8 V
DAC(VID0-VID4) Input High Voltage 2.0 - - V
DACOUT Voltage Accuracy -1.0 - +1.0 %
Bandgap Reference Voltage V

BG

Bandgap Reference Tolerance -2.5 - +2.5 %
LINEAR REGULATORS (OUT2, OUT3, AND OUT4)
Regulation (All Linears) -3- %
VSEN2 Regulation Voltage VREG
VSEN2 Regulation Voltage VREG
VSEN3 Regulation Voltage VREG
VSEN4 Regulation Voltage VREG
Under-Voltage Level (VSEN/VREG) VSEN
Under-Voltage Hysteresis (VSEN/VREG) VSEN Falling - 7 - %
Output Drive Current (All Linears) VAUX-V

UGATE, LGATE, DRIVE2, DRIVE3, and
DRIVE4 Open

OCSET
OCSET
OCSET
OCSET

RT = OPEN 185 200 215 kHz

RT = Open - 1.9 - V

SELECT < 0.8V - 1.5 - V

2

SELECT > 2.0V - 3.3 - V

2
3
4

VSEN Rising - 75 - %

UV

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

-9- mA

= 4.5V - - 10.4 V
= 4.5V 8.2 - - V
= 4.5V - 2.5 - V
= 4.5V - 0.5 - V

- 1.265 - V

- 1.5 - V

- 1.8 - V

> 0.6V 20 40 - mA

DRIVE

P-P

2-299

HIP6021

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain -88- dB
Gain-Bandwidth Product GBWP - 15 - MHz
Slew Rate SR COMP = 10pF - 6 - V/µs

PWM CONTROLLER GATE DRIVER

UGATE Source I
UGATE Sink R
LGATE Source I
LGATE Sink R

UGATE

UGATEVGATE-PHASE

LGATE

LGATE

VCC = 12V, V

VCC = 12V, V
V

= 1V - 1.4 3.0 Ω

LGATE

PROTECTION

VSEN1 Over-Voltage (VSEN1/DACOUT) VSEN1 Rising - 115 120 %
FAULT Sourcing Current I
OCSET1 Current Source I
Soft-Start Current I

OVP

OCSET

SS

V

FAULT/RT

V

OCSET

= 2.0V - 8.5 - mA

= 4.5V

POWER GOOD

VSEN1 Upper Threshold

VSEN1 Rising 108 - 110 %

(VSEN1/DACOUT)
VSEN1 Under-Voltage

VSEN1 Rising 92 - 94 %

(VSEN1/DACOUT)
VSEN1 Hysteresis (VSEN1/DACOUT) Upper/Lower Threshold - 2 - %
PGOOD Voltage Low V

PGOODIPGOOD

= -4mA - - 0.8 V

= 6V - 1 - A

UGATE

= 1V - 1.7 3.5 Ω

= 1V - 1 - A

LGATE

DC

170 200 230 µA

-28- µA

Typical Performance Curves

1000

100

RESISTANCE (kΩ)

10

RT PULLUP
TO +12V

RT PULLDOWN TO V

10 100 1000

SWITCHING FREQUENCY (kHz)

FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

SS

100

C
VIN = 5V

80

VCC = 12V

60

(mA)

CC

I

40

20

0

100 200 300 400 500 600 700 800 900 1000

UGATE1

= C

= C

UGATE2

SWITCHING FREQUENCY (kHz)

LGATE1

= C

C = 4800pF

C = 3600pF

C = 1500pF

C = 660pF

2-300

HIP6021

Functional Pin Descriptions

VCC (Pin 28)

Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.

GND (Pin 17)

Signal groundfor the IC.All voltage levelsare measured with
respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.

VAUX (Pin 16)

This pin provides boost current for the linear regulators’
output drives in the event bipolar NPN transistors (instead
of N-channel MOSFETs) are employed as pass elements.
The voltage at this pin is monitored for power-on reset
(POR) purposes.

SS (Pin 12)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the
soft-start interval of the converter.

FAULT / RT (Pin 13)

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
200kHz switching frequency is increased according to the
following equation:

510

Fs 200KHz

×

-------------------- -+≈

RTkΩ()

Conversely, connecting a resistor from this pin to VCC
reduces the switching frequency according to the following
equation:

410

Fs 200KHz

×

-------------------- -–≈

RTkΩ()

Nominally, the voltage at this pin is 1.26V. In the event of an
over-voltage or over-current condition, this pin is internally
pulled to VCC.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
synchronous regulator output is not within ±10% of the
DACOUT reference voltageorwhen any of the other outputs
are below their under-voltage thresholds.

The PGOOD output is open for ‘11111’ VID code.

SD (Pin 9)

This pin shuts down all the outputs. A TTL-compatible, logic
level high signal applied at this pin immediately discharges

) from this pin to GND, the nominal

T

6

(RT to GND)

7

(RT to 12V)

the soft-start capacitor, disabling all the outputs. Dedicated
internal circuitry insures the core output voltage does not go
negative during this process. When re-enabled, the IC
undergoes a newsoft-start cycle. Leftopen,thispinispulled
low by an internal pull-down resistor, enabling operation.

FIX (Pin 2)

Grounding this pin bypasses the internal resistor dividers
that set the output voltage of the 1.5V and 1.8V linear
regulators. This way, the output voltage of the two regulators
can be adjusted from 1.26V up to the input voltage (+3.3V or
+5V) by way of an external resistor divider connected at the
corresponding VSEN pin. The new output voltage set by the
external resistor divider can be determined using the
following formula:

R



V

where R

OUT

1.265V 1

is the resistor connected from VSEN to the

OUT

output of the regulator, and R

OUT

---------------- -+

×=



R



GND

GND

is the resistor connected
from VSEN to ground. Left open, the FIX pin is pulled high,
enabling fixed output voltage operation.

VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)

VID0-4 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference(DACOUT). The level of DACOUT sets the
microprocessor core converter output voltage, as well as the
coresponding PGOOD and OVP thresholds.

OCSET (Pin 23)

Connect a resistor from this pin to the drain of the respective
upper MOSFET. This resistor, an internal 200µA current
source, and the upper MOSFET’s on-resistance set the
converter over-current trip point. An over-current trip cycles
the soft-start function.

The voltageat this pin is monitored forpower-on reset (POR)
purposes and pulling this pin low with an open drain device
will shutdown the IC.

PHASE (Pin 26)

Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin represents the gate drive return
current path and is used to monitor the voltage drop across
the upper MOSFET for over-current protection.

UGATE (Pin 27)

Connect UGATE pin tothePWMconverter’s upperMOSFET
gate. This pin provides the gate drive for the upper MOSFET.

LGATE (Pin 25)

Connect LGATE to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.

COMP and FB (Pin 20, and 21)

COMP and FB are the available e xternal pins of the PWM
converter error amplifier.The FB pin is the inverting input of the

2-301

HIP6021

error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM conv erter .

VSEN1 (Pin 22)

This pin is connectedtothePWM converter’s output voltage.
The PGOOD and OVP comparator circuits use this signal to
report output voltage status and for over- voltage protection.

DRIVE2 (Pin 1)

Connect this pin tothegateof an external MOSFET. This pin
provides the drive for the AGP regulator’s pass transistor.

VSEN2 (Pin 10)

Connect this pin to the output of the AGP linear regulator.
The voltage at this pin is regulated to the level
predetermined by the logic-level status of the SELECT pin.
This pin is also monitored for under-voltage events.

SELECT (Pin 11)

This pin determines the output voltage of the AGP bus linear
regulator. A low TTL input sets the output voltage to 1.5V,
while a high input sets the output voltage to 3.3V.

DRIVE3 (Pin 18)

Connect this pin tothegateof an external MOSFET. This pin
provides the drive for the 1.5V regulator’s pass transistor.

VSEN3 (Pin 19)

Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for under-voltage events.

DRIVE4 (Pin 15)

Connect this pin tothegateof an external MOSFET. This pin
provides the drive for the 1.8V regulator’s pass transistor.

VSEN4 (Pin 14)

Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.

Description

Operation

The HIP6021 monitors and precisely controls 4 output
voltage levels(Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). It is
designed for microprocessor computer applications with

3.3V, 5V, and 12V bias input from an ATX power supply.
The IC has a synchronous PWM controller and three linear
controllers. The PWM controller (PWM) is designed to
regulate the microprocessor core voltage (V
controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter configuration and
regulates the microprocessor core voltage to a level
programmed by the 5-bit digital-to-analog converter (DAC).
One of the linear controllers is designed to regulate the
advanced graphics port (AGP) bus voltage (V
digitally-programmable level of 1.5V or 3.3V. Selection of

OUT1

OUT2

). PWM

) to a

either output voltage is achieved by applying the proper
logic level at the SELECT pin. The remaining two linear
controllers supply the 1.5V GTL bus power (V
the 1.8V memory power (V
designed to employ an external pass transistor.

). All linear controllers are

OUT4

OUT3

) and

Initialization

The HIP6021 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12V
(+5V

) on the OCSET pin, and the 3.3V input voltage

IN

(+3.3V
equal to +5V
protection). The POR function initiates soft-start operation
after all supply voltages exceed their POR thresholds.

) at the VAUX pin. The normal level on OCSET is

IN

IN

) at the VCC pin, the 5V input voltage

IN

less a fixed voltage drop (see over-current

Soft-Start

The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
28µA current source charges an external capacitor (C
the SS pin to 4.5V. The PWM error amplifier reference input
(+ terminal) and output (COMP pin) are clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
slews from 1V to 4V, the output clamp allows generation of
PHASE pulses of increasing width that charge the output
capacitor(s). After the output voltage increases to
approximately 70% of the set value, the reference input
clamp slows the output voltage rate-of-rise and provides a
smooth transition to the final set voltage. Additionally, all
linear regulators’ reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.

Figure 3 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular wave form is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse-width on the PHASE pin
increases. The interval of increasing pulse-width continues
until each output reaches sufficient voltage to transfer
control to the inputreferenceclamp. If we considerthe2.5V
core output (V
During the interval between T2 and T3, the error amplifier
reference ramps to the final value and the converter
regulates the output a voltage proportional to the SS pin
voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.

The remaining outputs are also programmed to follow the
SS pin voltage. The PGOOD signal toggles ‘high’ when all
output voltage levels have exceeded their under-voltage
levels. See the Soft-Start Interval section under

) in Figure 3, this time occurs at T2.

OUT1

SS

)on

2-302

0V

0V

VOLTAGES

0V

PGOOD

SOFT-START

(1V/DIV)

V

OUT2

V

OUT1

V

OUT4

OUTPUT

(0.5V/DIV)

T1 T2 T3T0 T4

FIGURE 3. SOFT-START INTERVAL

TIME

V

OUT3

( = 3.3V)

(DAC = 2.5V)

( = 1.8V)

( = 1.5V)

Applications Guidelines for a procedure to determine the
soft-start interval.

Fault Protection

All fouroutputs are monitored and protectedagainstextreme
overload. A sustained overload on any output or an over­voltage on V
drives the FAULT/RT pin to VCC.

LUV

OC1

0.15V

SS

4V

OV

FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC

Figure 4 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. The over-current latch is set dependent
upon the states of the over-current (OC), linear under­voltage (LUV) and the soft-start signals. A window
comparator monitors the SS pin and indicates when C

output (VSEN1) disables all outputs and

OUT1

+

-

+

-

OVER-

CURRENT

LATCH

SRQ

UP

COUNTER

R

POR

INHIBIT

FAULT

LATCH

SRQ

VCC

FAULT

SS

is

HIP6021

fully charged to 4V (UP signal). An under-voltage on either
linear output (VSEN2, VSEN3, or VSEN4) is ignored until
after the soft-start interval (T4 in Figure 3). This allows
V

OUT2,VOUT3

up.Cyclingthe bias input voltage (+12V

, and V

to increase without fault at start-

OUT4

on the VCCpinoff

IN

then on) resets the counter and the fault latch.

Over-Voltage Protection

During operation, ashort on theupperMOSFET of the PWM
regulator (Q1) causes V

to increase. When the output

OUT1

exceedstheover-voltage threshold of 115% of DACOUT,the
over-voltage comparator trips to set the fault latch and turns
Q2 on. This blows the input fuse and reduces V

OUT1

. The

fault latch raises the FAULT/RT pin to VCC.
A separate over-voltage circuit provides protection during

the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored forvoltagesabove 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2 is driven on.

Over-Current Protection

All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s
on-resistance, r
against shorted output. All linear controllers monitor their
respective VSEN pins for under-voltage events to protect
against excessive currents.

Figure 5 illustrates the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the inductor (L
the OVER-CURRENT comparator trips when the voltage
across Q1 (i

D•rDS(ON)

ROCSET. This inhibits all outputs, discharges the soft-start
capacitor (C
the counter. C

) with a 10mA current sink, and increments

SS

SS

cycle with the error amplifiers clamped by soft-start. With
OUT1 still overloaded, the inductor current increases to trip
the over-current comparator. Again, this inhibits all outputs,
but the soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start
cycle repeats at T3 and trips the over-current comparator.
The SS pin voltage increases to 4V at T4 and the counter
increments to 3. This sets the fault latch to disable the
converter. The fault is reported on the FAULT/RT pin.

The linear controllers operate in the same way as the PWM
in response to over-current faults. The differentiating factor
for the linear controllers is that they monitor the VSEN pins
for under-voltage events. Should excessive currents cause
the voltage at the VSEN pins to fall below the linear under­voltage threshold, the LUV signal sets the over-current
latch if C
the C

is fully charged. Blanking the LUV signalduring

SS

charge interval allows the linear outputs to build

SS

abovethe under-voltage threshold duringnormaloperation.
Cycling the bias input power off then on resets the counter
and the fault latch.

to monitor the current for protection

DS(ON)

). At time T1,

OUT1

) exceeds the level programmed by

recharges at T2 and initiates a soft-start

2-303

HIP6021

FAULT

REPORTED

COUNT

= 2

TIME

COUNT

= 3

FAULT/RT

INDUCTOR CURRENT SOFT-START

10V

0V

4V

2V

0V

0A

COUNT

= 1

OVERLOAD

APPLIED

T1 T2 T3T0 T4

FIGURE 5. OVER-CURRENT OPERATION

A resistor (R

) programs the over-currenttrip level for

OCSET

the PWM converter. As shown in Figure 6, the internal
200µA current sink, I
R

OCSET(VSET

) that is referenced to VIN. The DRIVE

develops a voltage across

OCSET

signal enables the over-current comparator (OVER­CURRENT). When the voltage across the upper MOSFET
(V

) exceeds V

DS

set the over-current latch. Both V
referenced to V
helps V

OCSET

, the over-current comparator trips to

SET

and a small capacitor across R

IN

and VDS are

SET

OCSET

track the variations of VIN due to MOSFET
switching. The over-current function will trip at a peak
inductor current (I

I

OCSETROCSET

I

PEAK

--------------------------------------------------- -

=

r

DS ON()

OVER-CURRENT TRIP:

VDSV

>

× I

iDr

DS ON()

OVER-

CURRENT

OC

PWM

+

-

CONTROL

FIGURE 6. OVER-CURRENT DETECTION

×

determined by:

PEAK)

SET

×>

OCSETROCSET

OCSET

I

OCSET

200µA

DRIVE

GATE

R

OCSET

V

SET

VCC

UGATE

PHASE

V

PHASEVINVDS

V

OCSETVINVSET

+

VIN = +5V

i

D

+

V

DS

–=

–=

The OC trip point varies with MOSFET’s r

DS(ON)

temperature variations. To avoid over-currenttripping in the
normal operating load range, determine the R

OCSET

resistor from the equation above with:

1. The maximum r

2. The minimum I

3. Determine I

PEAK

DS(ON)
OCSET

at the highest junction temperature.

from the specification table.

for I

PEAK>IOUT(MAX)

+(∆I)/2, where

∆I is the output inductor ripple current.

For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.

OUT1 Voltage Program

The output voltage of the PWM converter is programmed to
discrete levels between 1.3V
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program aninternal voltagereference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter. The levelof
DACOUT also sets the PGOOD and OVP thresholds. Table
1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, because they are
internally pulled up to an internal voltage of about 5V by a
10µA current source. Changing the VID inputs during
operation isnotrecommendedand could toggle the PGOOD
signal and exercise the over-voltage protection. ‘11111’ VID
pin combination disables the IC and opens the PGOOD pin.

TABLE 1. OUT1 VOLTAGE PROGRAM

PIN NAME NOMINAL

011111.30

011101.35

011011.40

011001.45

010111.50

010101.55

010011.60

010001.65

001111.70

001101.75

001011.80

001001.85

000111.90

000101.95

000012.00

000002.05
11111 0

and 3.5VDC. This output

DC

DACOUT

VOLTAGEVID4 VID3 VID2 VID1 VID0

2-304

TABLE 1. OUT1 VOLTAGE PROGRAM (Continued)

PIN NAME NOMINAL

DACOUT

VOLTAGEVID4 VID3 VID2 VID1 VID0

111102.1

111012.2

111002.3

110112.4

110102.5

110012.6

110002.7

101112.8

101102.9

101013.0

101003.1

100113.2

100103.3

100013.4

100003.5

NOTE: 0= connected to GND, 1 = openor connected to 5Vthrough
pull-up resistors

OUT2 Voltage Selection

The AGP regulator output voltage is internally set to one of
two discrete levels, based on the status of the SELECT pin.
SELECT pin is internally pulled ‘high’, such that left open,
the AGP output voltage is by default set to 3.3V. The other
discrete setting available is 1.5V, which can be obtained by
grounding the SELECT pin using a jumper or another
suitable method capable of sinking a few tens of
microamperes. The status of the SELECT pin cannot be
changed during operation of the IC without immediately
causing a fault condition.

OUT3 and OUT4 Voltage Adjustability

The GTL bus voltage (1.5V, OUT3) and the chip set and/or
cache memory voltage (1.8V, OUT4) are internally set for
simple, low-cost implementation in typical Intel motherboard
architectures. However, if different voltage settings are
desired for these two outputs, the FIX pin provides the
necessary adaptability. Left open(NC),thispin sets the fixed
output voltages described above. Grounding this pin allows
both output voltages to be set by means of external resistor
dividers as shown in Figure 7.

HIP6021

R

R

--------+
R

P3

S
P

VAUX

DRIVE3

VSEN3

HIP6021

DRIVE4

VSEN4

FIX

+3.3V

IN

Q4

V

OUT3

R

C

OUT3

Q5

V

OUT4

C

OUT4

V

OUTVBG

FIGURE 7. ADJUSTING THE OUTPUT VOLTAGE OF

OUTPUTS 3 AND 4

S3

R

S4

R

P4



1

×=




Application Guidelines

Soft-Start Interval

Initially, the soft-start function clamps the error amplifier’s
output of the PWM converter.This generates PHASE pulses
of increasing width that charge the output capacitor(s). After
the output voltageincreasestoapproximately 70% of the set
value, the referenceinput of the error amplifier is clamped to
a voltage proportional to the SS pin voltage. The resulting
output voltages start-up as shown in Figure 3.

The soft-start function controls the output voltage rate of rise
to limit thecurrentsurgeat start-up.The soft-startintervaland
the surge current are programmed by the soft-start capacitor,
C

. Programming a faster soft-start interval increases the

SS

peak surge current. The peak surge current occurs during the
initial output voltage rise to 70% of the set value.

Shutdown

The HIP6021 features a dedicated shutdown pin (SD). A
TTL-compatible, logic high signal applied to this pin shuts
down (disables)allfour outputs and discharges the soft-start
capacitor. Following a shutdown, a logic low signal
re-enables the outputs through initiation of a new soft-start
cycle. Leftopenthispin will asses a logic low state,duetoits
internal pull-down resistor,thus enabling normal operation of
all outputs.

2-305

The PWM output does not switch until the soft-start voltage
(V

) exceeds the oscillator’svalley voltage. The references

SS

on each linear’s error amplifier are clamped to the soft-start
voltage. Holding the SS pin low (with an open drain or
collector signal) turns off all four regulators.

The ‘11111’ VID code also shuts down the IC.

HIP6021

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn­off transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes. See the Application Note
ANTBD for evaluation board drawings of the component
placement and printed circuit board.

There are two sets of critical components in a DC-DC
converter using a HIP6020 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.

wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A
peak currents.

PWM Controller Feedback Compensation

The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.

Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

) is regulated to the Reference voltage level. The

OUT

referencevoltagelevelistheDAC outputvoltage (DACOUT).
The error amplifier (Error Amp) output (V

) is compared

E/A

with the oscillator (OSC) triangular wave to provide a pulse­width modulated (PWM) wave with an amplitude of V

IN

at
the PHASE node.ThePWMwave is smoothed by the output
filter (L

and CO).

O

The modulator transfer function is the small-signal transfer
function of V

OUT/VE/A

Gain, given by V
with a double pole break frequency at F
F

.

ESR

. This function is dominated by a DC

IN/VOSC

, and shaped by the output filter,

and a zero at

LC

Modulator Break Frequency Equations

F

--------------------------------------- -= F

LC

2π LOCO××

1

ESR

-----------------------------------------=

2π ESR CO××

1

The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high­frequency ceramicdecouplingcapacitors,close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.

The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C

SS

. Locate
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node, since the internal current source is only 28µA.

A multi-layer printed circuit board is recommended. Figure
8shows the connections of the critical components in the
converter. Note that the capacitors C

and C

IN

OUT

each
represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages,
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal

The compensation network consists of the error amplifier
(internal to the HIP6021) and the impedance networks Z

IN

and ZFB. The goalofthe compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f
is the difference between the closed loop phase at f

) and adequate phase margin. Phase margin

0dB

0dB

and
180 degrees. The equations below relate the compensation
network’spoles,zerosandgain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1

3. Place 2

4. Place 1

5. Place 2

ST

Zero Below Filter’s Double Pole (~75% FLC)

ND

Zero at Filter’s Double Pole

ST

Pole at the ESR Zero

ND

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

2-306

HIP6021

L

IN

IN

OUT2

LOAD

OUT3

LOAD

+3.3V

IN

C

C

IN

C

IN

OUT2

OUT3

Q3

C

Q4

SS

+12V

C

VCC

GNDVCC

OCSET1

DRIVE2

UGATE1

PHASE1

LGATE1

SS

HIP6021

DRIVE4

DRIVE3

PGND

KEY

ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE

C

OCSET1

Q2

Q5

R

OCSET1

Q1

L

OUT1

C

CR1

C

OUT4

OUT1

V

+5V

+3.3V

V

V

FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

V

OUT1

OUT4

LOAD

LOAD

Compensation Break Frequency Equations

F

Z1

F

Z2

1

-----------------------------------=

2π R× 2C1×

-------------------------------------------------------=

2π R1 R3+()C3××

1

F

P1

F

P2

-------------------------------------------------------=

2π R

-----------------------------------=

2π R× 3C3×

Figure 10 shows an asymptotic plot of the DC-DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak dependent on the quality factor (Q) of
the output filter, which is not shown in Figure 9. Using the
above guidelines should yield a Compensation Gain similar
to the curve plotted. The open loop error amplifier gain
bounds the compensation gain. Check the compensation
gain at F

with the capabilities of the error amplifier. The

P2

Closed Loop Gain is constructed on the log-log graph of
Figure 10 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.

The compensation gain uses external impedance networks
Z

and ZINto provideastable, high bandwidth (BW) overall

FB

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.

1

C1 C2×



----------------------

××

2



C1 C2+

1

V

IN

L

O

PHASE

(PARASITIC)

IN

Z

FB

Z

IN

C3

R1

FB

∆V

OSC

OSC

PWM

COMP

-

+

Z

FB

V

E/A

-

+

ERROR
AMP

DETAILED COMPENSATION COMPONENTS

COMP

DRIVER

DRIVER

Z

REFERENCE

C2

C1

R2

-

+

HIP6021

DACOUT

FIGURE 9. VOLTAGE-MODEBUCK CONVERTER

COMPENSATION DESIGN

C

ESR

R3

O

V

OUT

V

OUT

OPEN LOOP

ERROR AMP GAIN

V



IN

------------

20

log



V



PP

COMPENSATION

GAIN

CLOSED LOOP

GAIN

10M1M100K10K1K10010

100

80

60

40

20

GAIN (dB)

0

-20
MODULATOR

-40

-60

F

Z1

R2



------- -

log

20



R1

GAIN

F

Z2

F

F

LC

ESR

FREQUENCY (Hz)

F

F

P1

P2

FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

Component Selection Guidelines

Output Capacitor Selection

The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters requireanoutput capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.

2-307

HIP6021

PWM Output Capacitors

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physicallypossible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’s edge. An aluminum electrolytic capacitor’s ESR
value is related to the case size with lower ESR available in
larger case sizes.However, the equivalentseriesinductance
(ESL) of these capacitors increases with case size and can
reduce the usefulness of the capacitor to high slew-rate
transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure
the capacitor’simpedance with frequency to selectasuitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.

Linear Output Capacitors

The output capacitors for the linear regulators provide
dynamic load current. The linear controllers use dominant
pole compensation integratedintothe error amplifier and are
insensitive to output capacitor selection. Output capacitors
should be selected for transient load regulation.

PWM Output Inductor Selection

The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient.Theinductor value determines the converter’s
ripple current and the ripple voltage is a functionoftheripple
current. The ripple voltage and current are approximated by
the following equations:

∆I

V

–

INVOUT

------------------------------- -

F

S

V

OUT

--------------- -

×=

L×

V

IN

∆ I∆ ESR×=

V

OUT

HIP6021 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

LOI

×

TRAN

t

RISE

where: I

------------------------------- -=
–

V

INVOUT

is the transient load current step, t

TRAN

t

FALL

response time to the application of load, and t

LOI

×

------------------------------ -=

V

TRAN

OUT

RISE

FALL

is the

is the
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings abovethe maximum input voltage andlargest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.

For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.

Increasing the valueof inductance reduces the ripple current
and voltage. However, the large inductance values increase
the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the

2-308

MOSFET Selection/Considerations

The HIP6021 requires 5 external transistors. Two N-channel
MOSFETs are used in the synchronous-rectified buck
topology of PWM1 converter. It is recommended that the
AGPlinearregulatorpass element be a N-channel MOSFET
as well. The GTL and memory linear controllers can also

HIP6021

each drive a MOSFET or a NPN bipolar as a pass transistor.
All these transistors should be selected based upon
r

DS(ON)

, current gain, saturation voltages, gate supply

requirements, and thermal management considerations.

PWM MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The powerdissipationincludestwo
loss components; conduction loss and switching loss.These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.

The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse­recovery of the lower MOSFET’s body diode. The gate­charge losses are dissipated by the HIP6021 and don't heat
the MOSFETs. However, large gate-charge increases the
switching time, t
switchinglosses.Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

P

UPPER

P

LOWER

I

------------------------------------------------------------

which increases the upper MOSFET

SW

2

r

× V

O

2

I

r

× VINV

O

---------------------------------------------------------------------------------=

×

DS ON()

V

IN

DS ON()

V

IN

OUT

I

OVIN

----------------------------------------------------+=

–()×

OUT

× tSW× FS×

2

+12V

VCC

HIP6021

UGATE
PHASE

-

+

FIGURE 11. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

LGATE
PGND

GND

+5V OR LESS

Q1

Q2

CR1

NOTE:
V

GS

NOTE:
V

GS

≈ V

≈ V

CC

CC

-5V

Linear Controller Transistor Selection

The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:

P

LINEARIOVINVOUT

Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.

When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating VCE is sufficiently large to provide the desired
output load current when the base is fed with the minimum
driver output current.

–()×=

The r

is different for the two equations above even if

DS(ON)

the same device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 11 shows the gate drive where the
upper MOSFET’s gate-to-source voltage is approximately
VCC less theinputsupply.For +5Vmainpower and+12VDC
for the bias, the gate-to-source voltage of Q1 is 7V. The
lowergatedrivevoltage is +12VDC.Alogic-level MOSFET is
a good choice forQ1 and a logic-level MOSFETcanbeused
for Q2 if its absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.

Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency could drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.

2-309

HIP6021

HIP6021 DC-DC Converter Application Circuit

Figure 12 shows an application circuit of a power supply for a
microprocessor computer system. The power supply provides
the microprocessor core voltage (VOUT1), the AGP bus
voltage (VOUT2), the GTL b us v oltage (VOUT3), and the
memory voltage (VOUT4) from +3.3V, +5VDC, and +12VDC.

+12V

IN

L1

+5V

GND

+3.3V

IN

IN

1µH

C1-6

6x1000µF

FAULT/RT

+

VAUX

VCC

28

13
16

For detailed information on the circuit, including a Bill-of­Materials and circuit board description, see Application Note
AN9836. AlsoseeIntersil’s web page (http://www.intersil.com)
or IntersilAnsw erFAX (407-724-7800) DocumentNo .99836 for
the latest information.

C7
1µF

23

8

OCSET

PGOOD

C8

1000pF

R1

1.0K

C9
1µF

POWERGOOD

V

OUT2

(3.3V or 1.5V)

TYPEDET

HUF76107D3S

V

OUT3

(1.5V)

V

OUT4

(1.8V)

+

C10,11

2x1000µF

Q4

+

C23,24

2x1000µF

+

Q5

C25,26

2x1000µF

HUF76107D3S

Q3

HUF76121D3S

DRIVE2

VSEN2

SELECT

DRIVE3

VSEN3

DRIVE4

VSEN4

SD

FIX

1

10

11

18

19

15

14

9

2

U1

HIP6021

17

GND

27
26

25
24

22

21

20

12

7
6

5
4
3

UGATE

PHASE

LGATE
PGND

VSEN1
FB

COMP

VID0
VID1

VID2
VID3
VID4

SS

C21
10pF

C22

2.7nF

C27

0.1µF

Q1,2

2xHUF76143S3S

R3

1.62k

R4

150K

499K

R5

L2

4.2µH

C12-19

8x1000µF
R2

10.2K

0.22µF

C20

V

OUT1

(1.3V-3.5V)

+

FIGURE 12. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right tomake changes in circuit designand/or specifications at any timewith­out notice. Accordingly, the reader is cautioned to verify that data sheets are current bef ore placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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