Datasheet HI-774, HI-674A, HI-574A Datasheet (Intersil Corporation)

August 1997

HI-574A, HI-674A,

HI-774

Complete, 12-Bit A/D Converters

with Microprocessor Interface

Features

• Complete 12-Bit A/D Converter with Reference and Clock

• Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface

• Bus Access Time. . . . . . . . . . . . . . . . . . . . . . . . . .150ns

• No Missing Codes Over Temperature

• Minimal Setup Time for Control Signals

• Fast Conversion Times

- HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs

- HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15µs

- HI-774 (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9µs

• Digital Error Correction (HI-774)

• Low Noise, via Current-Mode Signal
Transmission Between Chips

• Byte Enable/Short Cycle (A

Input)

O

- Guaranteed Break-Before-Make Action, Eliminating

Bus Contention During Read Operation. Latched by
Start Convert Input (T o Set the Conversion Length)

• Supply Voltage. . . . . . . . . . . . . . . . . . . . . ±12V to ±15V

Applications

• Military and Industrial Data Acquisition Systems

• Electronic Test and Scientific Instrumentation

• Process Control Systems

Description

The HI-X74(A) is a complete 12-bit, Analog-to-Digital
Converter, including a +10V reference clock, three-state out­puts and a digital interface for microprocessor control. Succes­sive approximation conversion is performed by two monolithic
dice housed in a 28 lead package. The bipolar analog die fea­tures the Intersil Dielectric Isolation process, which provides
enhanced AC performance and freedom from latch-up.

Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital ICs. Also, the clock oscillator is current
controlled for excellent stability over temperature.

The HI-X74(A) offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.

Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW (HI-574A/674A) and 390mW (HI-774) at
12V. All models are available in sidebrazed DIP, PDIP, and
CLCC. For additional HI-Rel screening including 160 hour b urn­in, specify “-8” suffix. For MIL-STD-883 compliant parts, request
HI-574A/883, HI-674A/883, and HI-774/883 data sheets.

Pinouts

(PDIP, SBDIP)

TOP VIEW

+5V SUPPL Y, V

DATA MODE SEL, 12/

CHIP SEL, CS

BYTE ADDR/SHORT

CYCLE, A

READ/CONVERT , R/

CHIP ENABLE, CE

+12V/+15V SUPPL Y, V

+10V REF , REF OUT

ANALOG

COMMON, AC

REFERENCE INPUT

-12V/-15V SUPPLY , V
BIPOLAR OFFSET

BIP OFF

10V INPUT
20V INPUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

LOGIC

CC

EE

1
2

8

3
4

O

5

C

6
7
8

9
10
11
12
13
14

28

STATUS, STS

27

DB11

26

DB10

25

DB9

24

DB8

23

DB7

22

DB6

21

DB5

20

DB4

19

DB3

18

DB2

17

DB1

16

DB0
DIG COMMON,

15

DC

MSB

DIGITAL
DATA
OUTPUTS

LSB

READ CONVERT, R/C

CHIP ENABLE, CE
+15V SUPPLY, V

+10V REFERENCE,

ANALOG COMMON, AC

REFERENCE INPUT,

REF OUT

-15V SUPPLY, V

BIPOLAR OFFSET,

6-952

REF IN

BIP OFF

NC
NC

CC

EE

NC

6 3

7
8

9
10
11
12
13
14
15
16
17

(CLCC)

TOP VIEW

BYTE ADDRESS/

NC

NC

4

NCNCNC

10V

20V

O

CS

SHORT CYCLE, A

CHIP SELECT,

SELECT, 12/8

DATA MODE
25

LOGIC

+5V SUPPLY, V

STATUS, STS

DB11, MSB

DB10

NC

NC

(LSB) DB0

NC

40414243

39
38
37
36
35
34
33
32
31
30
29

2827262524232221201918

DB1

1

NC

44

DC

DIG

COMMON,

NC

File Number 3096.4

NC
NC
DB9
DB8
DB7
DB6
DB5
DB4
DB3
NC
DB2

HI-574A, HI-674A, HI-774

Ordering Information

TEMPERA TURE RANGE

PART NUMBER INL

HI3-574AJN-5 ±1.0 LSB 0 to 75 28 Ld PDIP E28.6
HI3-574AKN-5 ±0.5 LSB 0 to 75 28 Ld PDIP E28.6
HI3-574ALN-5 ±0.5 LSB 0 to 70 28 Ld PDIP E28.6
HI1-574AJD-5 ±1.0 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-574AKD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-574ALD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-574ASD-2 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574ATD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574AUD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574ASD/883 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574ATD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574AUD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI4-574ASE/883 ±1.0 LSB -55 to 125 44 Ld CLCC J44.A
HI4-574ATE/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI4-574AUE/883
HI3-674AJN-5 ±1.0 LSB 0 to 75 28 Ld PDIP E28.6
HI3-674AKN-5 ±0.5 LSB 0 to 75 28 Ld PDIP E28.6
HI3-674ALN-5
HI1-674AJD-5 ±1.0 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-674AKD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-674ALD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-674ASD-2 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674ATD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674AUD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674ASD/883 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674ATD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674AUD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI4-674ASE/883 ±1.0 LSB -55 to 125 44 Ld CLCC J44.A
HI4-674ATE/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI4-674AUE/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI3-774J-5
HI3-774K-5
HI1-774J-5
HI1-774K-5
HI1-774U-2
HI1-774T/883
HI4-774S/883
HI4-774T/883
HI4-774U/883

±0.5 LSB

±0.5 LSB

±1.0 LSB 0 to 75 28 Ld PDIP E28.6
±0.5 LSB 0 to 75 28 Ld PDIP E28.6
±1.0 LSB 0 to 75 28 LdSBDIP
±0.5 LSB 0 to 75 28 LdSBDIP
±0.5 LSB -55 to 125 28 Ld SBDIP
±0.5 LSB -55 to 125 28 Ld SBDIP
±1.0 LSB -55 to 125 44 Ld CLCC
±0.5 LSB -55 to 125 44 Ld CLCC
±0.5 LSB -55 to 125 44 Ld CLCC

(oC) PACKA GE PKG. NO.

-55 to 125 44 Ld CLCC J44.A

0 to 75 28 Ld PDIP E28.6

D28.6
D28.6
D28.6
D28.6
J44.A
J44.A
J44.A

6-953

Functional Block Diagram

HI-574A, HI-674A, HI-774

BIT OUTPUTS

MSB LSB

12/8

CS
A

O

R/C

CE

IN

V

REF

V

OUT

REF

CONTROL

LOGIC

OSCILLATOR

DIGITAL CHIP

ANALOG CHIP

+10V

REF

THREE-STATE BUFFERS AND CONTROL

POWER-UP RESET

CLK

12 BITS

10K

+

-

5K

NIBBLE B (NOTE) NIBBLE C (NOTE)NIBBLE A (NOTE)

12 BITS

SAR

DAC

10K

STROBE

5K

5K

-

COMP

+

2.5K

V

LOGIC

DIGITAL
COMMON

STS

V

CC

V

EE

ANALOG

COMMON

NOTE: “Nibble” is a 4-bit digital word.

BIP

OFF

20V

INPUT

10V

INPUT

6-954

HI-574A, HI-674A, HI-774

Absolute Maximum Ratings Thermal Information

Supply Voltage

VCC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V

VEE to Digital Common. . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V

V

to Digital Common. . . . . . . . . . . . . . . . . . . . . . 0V to +7V

LOGIC

Analog Common to Digital Common±1V

Control Inputs

(CE, CS, AO, 12/8, R/C) to Digital Common . . -0.5V to V

Analog Inputs

(REFIN, BIPOFF, 10VIN) to Analog Common. . . . . . . . . . ±16.5V

20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V

REFOUT . . . . Indefinite Short To Common, Momentary Short To V

LOGIC

+0.5V

Operating Conditions

Temperature Range

HI3-574AxN-5, HI1-574AxD-5 . . . . . . . . . . . . . . . . . .0oC to 75oC

HI3-674AxN-5, HI1-674AxD-5 . . . . . . . . . . . . . . . . . .0oC to 75oC

HI3-774xN-5, HI1-774xD-5. . . . . . . . . . . . . . . . . . . . .0oC to 75oC

HI1-574AxD-2, HI1-674AxD-2, HI1-774xD-2 . . . . -55oC to 125oC

DC and Transfer Accuracy Specifications Typical at 25

Unless Otherwise Specified

PARAMETER

DYNAMIC CHARACTERISTICS

Resolution (Max) 12 12 12 Bits
Linearity Error

25oC (Max) ±1 ±1/
0oC to 75oC (Max) ±1 ±1/

Max Resolution For Which No Missing Codes Is Guaranteed

25oC HI-574A, HI-674A 12 12 12 Bits

HI-774 11 12 12 Bits

T

to T

MIN

MAX

Unipolar Offset (Max)

Adjustable to Zero ±2 ±1.5 ±1 LSB

Bipolar Offset (Max)

VIN = 0V (Adjustable to Zero) ±4 ±4 ±3 LSB
VIN = -10V ±0.15 ±0.1 ±0.1 % of FS

Full Scale Calibration Error

25oC (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
(Adjustable to Zero)

T
T

MIN
MIN

to T
to T

(No Adjustment At 25oC) ±0.475 ±0.375 ±0.20 % of FS

MAX

(With Adjustment To Zero 25oC) ±0.22 ±0.12 ±0.05 % of FS

MAX

HI-574A, HI-674A 11 12 12 Bits
HI-774 11 12 12 Bits

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

CLCC Package . . . . . . . . . . . . . . . . . . 65 14

SBDIP Package. . . . . . . . . . . . . . . . . . 60 18

HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5 65 N/A

Maximum Junction Temperature

HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . . . . . . . . 150oC

HI1-574AxD-2, HI1-574AxD-5. . . . . . . . . . . . . . . . . . . . . . .175oC

HI1-674AxD-2, HI1-674AxD-5. . . . . . . . . . . . . . . . . . . . . . .175oC

HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . . . . . . . . .175oC

Maximum Storage Temperature Range

CC

HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . .-40oC to 85oC

HI1-574AxD-2, HI1-574AxD-5. . . . . . . . . . . . . . . .-65oC to 150oC

HI1-674AxD-2, HI1-674AxD-5. . . . . . . . . . . . . . . .-65oC to 150oC

HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC

Die Characteristics

Transistor Count

HI-574A, HI-674A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117

HI-774 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2117

o

C with VCC = +15V or +12V, V

TEMPERATURE RANGE

-5 (0oC to 75oC)

2
2

±0.25 ±0.25 ±0.15 % of FS

= +5V, VEE = -15V or -12V,

LOGIC

±1/

2

±1/

2

UNITSJ SUFFIX K SUFFIX L SUFFIX

LSB
LSB

6-955

HI-574A, HI-674A, HI-774

DC and Transfer Accuracy Specifications Typical at 25

o

C with VCC = +15V or +12V, V

= +5V, VEE = -15V or -12V,

LOGIC

Unless Otherwise Specified (Continued)

TEMPERATURE RANGE

-5 (0oC to 75oC)

PARAMETER

Temperature Coefficients
Guaranteed Max Change, T

MIN

to T

(Using Internal Reference)

MAX

Unipolar Offset HI-574A, HI-674A ±2 ±1 ±1 LSB

HI-774 ±2 ±1 ±1 LSB

Bipolar Offset HI-574A, HI-674A ±2 ±1 ±1 LSB

HI-774 ±2 ±2 ±1 LSB

Full Scale Calibration HI-574A, HI-674A ±9 ±2 ±2 LSB

HI-774 ±9 ±5 ±2 LSB

Power Supply Rejection
Max Change In Full Scale Calibration

+13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V ±2 ±1 ±1 LSB
+4.5V < V

< +5.5V ±1/

LOGIC

2

±1/

2

±1/

2

-16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V ±2 ±1 ±1 LSB

ANALOG INPUTS

Input Ranges

Bipolar -5 to +5 V

-10 to +10 V

Unipolar 0 to +10 V

0 to +20 V

Input Impedance

10V Span 5K, ±25% Ω
20V Span 10K, ±25% Ω

POWER SUPPLIES

Operating Voltage Range

V

LOGIC

V

CC

V

EE

+4.5 to +5.5 V

+11.4 to +16.5 V

-11.4 to -16.5 V

Operating Current

I

LOGIC

7 Typ, 15 Max mA
ICC +15V Supply 11 Typ, 15 Max mA
IEE -15V Supply 21 Typ, 28 Max mA

Power Dissipation

±15V, +15V 515 Typ, 720 Max mW
±12V, +5V 385 Typ mW

Internal Reference Voltage

T

to T

MIN

MAX

Output Current, Available For External Loads (External Load Should

+10.00 ±0.05 Max V

2.0 Max mA

Not Change During Conversion).

UNITSJ SUFFIX K SUFFIX L SUFFIX

LSB

6-956

HI-574A, HI-674A, HI-774

DC and Transfer Accuracy Specifications Typical at 25

o

C with VCC = +15V or +12V, V

= +5V, VEE = -15V or -12V,

LOGIC

Unless Otherwise Specified

TEMPERATURE RANGE

-2 (-55oC to 125oC)

PARAMETER

UNITSS SUFFIX T SUFFIX U SUFFIX

DYNAMIC CHARACTERISTICS

Resolution (Max) 12 12 12 Bits
Linearity Error

25oC ±1 ±1/

2

±1/

2

-55oC to 125oC (Max) ±1 ±1 ±1 LSB

Max Resolution For Which No Missing Codes Is Guaranteed

25oC HI-574A, HI-674A 12 12 12 Bits

HI-774 11 12 12 Bits

T

MIN

to T

MAX

HI-574A, HI-674A 11 12 12 Bits
HI-774 11 12 12 Bits

Unipolar Offset (Max)

Adjustable to Zero HI-574A, HI-674A ±2 ±1.5 ±1 LSB

HI-774 ±2 ±2 ±1 LSB

Bipolar Offset (Max)

VIN = 0V (Adjustable to Zero) ±4 ±4 ±3 LSB
VIN = -10V ±0.15 ±0.1 ±0.1 % of FS

Full Scale Calibration Error

25oC (Max), With Fixed 50Ω Resistor From REF OUT To REF IN

±0.25 ±0.25 ±0.15 % of FS

(Adjustable To Zero)
T
T

MIN
MIN

to T
to T

(No Adjustment At 25oC) ±0.75 ±0.50 ±0.275 % of FS

MAX

(With Adjustment To Zero At 25oC) ±0.50 ±0.25 ±0.125 % of FS

MAX

Temperature Coefficients
Guaranteed Max Change, T

MIN

to T

(Using Internal Reference)

MAX

Unipolar Offset ±2 ±1 ±1 LSB
Bipolar Offset ±2 ±2 ±1 LSB
Full Scale Calibration ±20 ±10 ±5 LSB

Power Supply Rejection
Max Change In Full Scale Calibration

+13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V ±2 ±1 ±1 LSB
+4.5V < V

< +5.5V ±1/

LOGIC

2

±1/

2

±1/

2

-16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V ±2 ±1 ±1 LSB

ANALOG INPUTS

Input Ranges

Bipolar -5 to +5 V

-10 to +10 V

Unipolar 0 to +10 V

0 to +20 V

LSB

LSB

6-957

HI-574A, HI-674A, HI-774

DC and Transfer Accuracy Specifications Typical at 25

Unless Otherwise Specified (Continued)

PARAMETER

Input Impedance

10V Span 5K, ±25% Ω
20V Span 10K, ±25% Ω

POWER SUPPLIES

Operating Voltage Range

V

LOGIC

V

CC

V

EE

Operating Current

I

LOGIC

ICC +15V Supply 11 Typ, 15 Max mA
IEE -15V Supply 21 Typ, 28 Max mA

Power Dissipation

±15V, +15V 515 Typ, 720 Max mW
±12V, +5V 385 Typ mW

Internal Reference Voltage

T

to T

MIN

MAX

Output current, available for external loads (External load should not
change during conversion).

o

C with VCC = +15V or +12V, V

TEMPERATURE RANGE

-2 (-55oC to 125oC)

+4.5 to +5.5 V

+11.4 to +16.5 V

-11.4 to -16.5 V

7 Typ, 15 Max mA

+10.00 ±0.05 Max V

2.0 Max mA

= +5V, VEE = -15V or -12V,

LOGIC

UNITSS SUFFIX T SUFFIX U SUFFIX

Digital Specifications All Models, Over Full Temperature Range

PARAMETER MIN TYP MAX

Logic Inputs (CE, CS, R/C, AO, 412/8)

Logic “1” +2.4V - +5.5V
Logic “0” -0.5V - +0.8V
Current - ±0.1µA ±5µA
Capacitance - 5pF -

Logic Outputs (DB11-DB0, STS)

Logic “0” (I
Logic “1” (I
Logic “1” (I
Leakage (High-Z State, DB11-DB0 Only) - ±0.1µA ±5µA
Capacitance - 5pF -

Timing Specifications (HI-574A) 25

SYMBOL PARAMETER MIN TYP MAX UNITS

CONVERT MODE

t

DSC

- 1.6mA) - - +0.4V

SINK
SOURCE
SOURCE

- 500µA) +2.4V - -

- 10µA) +4.5V - -

o

C, Note 2, Unless Otherwise Specified

STS Delay from CE - - 200 ns

6-958

HI-574A, HI-674A, HI-774

Timing Specifications (HI-574A) 25

o

C, Note 2, Unless Otherwise Specified (Continued)

SYMBOL PARAMETER MIN TYP MAX UNITS

t

HEC

t

SSC

t

HSC

t

SRC

t

HRC

t

SAC

t

HAC

t

C

CE Pulse Width 50 - - ns
CS to CE Setup 50 - - ns
CS Low During CE High 50 - - ns
R/C to CE Setup 50 - - ns
R/C Low During CE High 50 - - ns
AO to CE Setup 0 - - ns
AO Valid During CE High 50 - - ns
Conversion Time 12-Bit Cycle T

8-Bit Cycle T

MIN

MIN

to T

to T

MAX

MAX

15 20 25 µs

10 13 17 µs

READ MODE

t
t

t

t

SSR

t

SRR

t

SAR

t

HSR

t

HRR

t

HAR

t

DD
HD
HL

HS

Access Time from CE - 75 150 ns
Data Valid After CE Low 25 - - ns
Output Float Delay - 100 150 ns
CS to CE Setup 50 - - ns
R/C to CE Setup 0 - - ns
AO to CE Setup 50 - - ns
CS Valid After CE Low 0 - - ns
R/C High After CE Low 0 - - ns
AO Valid After CE Low 50 - - ns
STS Delay After Data Valid 300 - 1200 ns

Timing Specifications (HI-674A) 25

o

C, Note 2, Unless Otherwise Specified

SYMBOL PARAMETER MIN TYP MAX UNITS

CONVERT MODE

t

DSC

t

HEC

t

SSC

t

HSC

t

SRC

t

HRC

t

SAC

t

HAC

t

C

STS Delay from CE - - 200 ns
CE Pulse Width 50 - - ns
CS to CE Setup 50 - - ns
CS Low During CE High 50 - - ns
R/C to CE Setup 50 - - ns
R/C Low During CE High 50 - - ns
AO to CE Setup 0 - - ns
AO Valid During CE High 50 - - ns
Conversion Time 12-Bit Cycle T

8-Bit Cycle T

MIN

MIN

to T

to T

MAX

MAX

91215µs
6810µs

READ MODE

t

DD

t

HD

t

HL

Access Time from CE - 75 150 ns
Data Valid After CE Low 25 - - ns
Output Float Delay - 100 150 ns

6-959

HI-574A, HI-674A, HI-774

Timing Specifications (HI-674A) 25

o

C, Note 2, Unless Otherwise Specified (Continued)

SYMBOL PARAMETER MIN TYP MAX UNITS

t

SSR

t

SRR

t

SAR

t

HSR

t

HRR

t

HAR

t

HS

Timing Specifications (HI-774) 25

CS to CE Setup 50 - - ns
R/C to CE Setup 0 - - ns
AO to CE Setup 50 - - ns
CS Valid After CE Low 0 - - ns
R/C High After CE Low 0 - - ns
AO Valid After CE Low 50 - - ns
STS Delay After Data Valid 25 - 850 ns

o

C, Into a load with RL = 3kΩ and CL = 50pF, Note 2, Unless Otherwise Specified

SYMBOL PARAMETER MIN TYP MAX UNITS

CONVERT MODE

t

DSC

t

HEC

t

SSC

t

HSC

t

SRC

t

HRC

t

SAC

t

HAC

t

C

STS Delay from CE - 100 200 ns
CE Pulse Width 50 30 - ns
CS to CE Setup 50 20 - ns
CS Low During CE High 50 20 - ns
R/C to CE Setup 50 0 - ns
R/C Low During CE High 50 20 - ns
AO to CE Setup 0 0 - ns
AO Valid During CE High 50 30 - ns
Conversion Time 12-Bit Cycle T

8-Bit Cycle T
12-Bit Cycle T
8-Bit Cycle T

MIN

MIN

MIN

MIN

to T

to T

to T

to T

(-5) - 8.0 9 µs

MAX

(-5) - 6.4 6.8 µs

MAX

(-2) - 9 11 µs

MAX

(-2) - 6.8 8.3 µs

MAX

READ MODE

t
t

t

t

SSR

t

SRR

t

SAR

t

HSR

t

HRR

t

HAR

t

DD
HD
HL

HS

Access Time from CE - 75 150 ns
Data Valid After CE Low 25 35 - ns
Output Float Delay - 70 150 ns
CS to CE Setup 50 0 - ns
R/C to CE Setup 0 0 - ns
AO to CE Setup 50 25 - ns
CS Valid After CE Low 0 0 - ns
R/C High After CE Low 0 0 - ns
AO Valid After CE Low 50 25 - ns
STS Delay After Data Valid - 90 300 ns

NOTES:

1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

2. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load.

6-960

HI-574A, HI-674A, HI-774

Pin Descriptions

PIN SYMBOL DESCRIPTION

1V
2 12/8 Data Mode Select - Selects between

3 CS Chip Select - Chip Select high disables

4AOByte Address/Short Cycle - See Table

5R/C Read/Convert - See Table 1 for

6 CE Chip Enable - Chip Enable low disables

7VCCPositive Supply (+12V/+15V)
8 REF OUT +10V Reference

9 AC Analog Common
10 REF IN Reference Input
11 V
12 BIP OFF Bipolar Offset
13 10V Input 10V Input - Used for 0V to 10V and -5V

14 20V Input 20V Input - Used f or 0V to 20V and -10V

15 DC Digital Common
16 DB0 Data Bit 0 (LSB)
17 DB1 Data Bit 1
18 DB2 Data Bit 2
19 DB3 Data Bit 3
20 DB4 Data Bit 4
21 DB5 Data Bit 5
22 DB6 Data Bit 6
23 DB7 Data Bit 7
24 DB8 Data Bit 8
25 DB9 Data Bit 9
26 DB10 Data Bit 10
27 DB11 Data Bit 11 (MSB)
28 STS Status Bit - Status high implies a

LOGIC

EE

Logic supply pin (+5V)

12-bit and 8-bit output modes.

the device.

1 for operation.

operation.

the device.

Negative Supply (-12V/-15V).

to +5V input ranges.

to +10V input ranges.

conversion is in progress.

Definitions of Specifications

Linearity Error

Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
used as “zero” occurs
the first code transition (all zeros to only the LSB “on”). “Full
scale” is defined as a level 1
sition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.

The HI-X74(A)K and L grades are guaranteed for maximum
nonlinearity of ±
analog value which falls exactly in the center of a given code
width will result in the correct digital output code. Values nearer
the upper or lower transition of the code width may produce the
next upper or lower digital output code. The HI-X74(A)J is
guaranteed to ±1 LSB max error. For this grade, an analog
value which falls within a given code width will result in either
the correct code for that region or either adjacent one.

Note that the linearity error is not user-adjustable.

Differential Linearity Error (No Missing Codes)

A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increas­ing sequence as the analog input level is increased. Thus
every code must hav e a finite width. F or the HI-X74(A)K and L
grades, which guarantee no missing codes to 12-bit resolu­tion, all 4096 codes must be present over the entire operating
temperature ranges. The HI-X74(A)J grade guarantees no
missing codes to 11-bit resolution over temperature; this
means that all code combinations of the upper 11 bits must be
present; in practice very few of the 12-bit codes are missing.

Unipolar Offset

The first transition should occur at a level
common. Unipolar offset is defined as the deviation of the
actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset tempera­ture coefficient specifies the maximum change of the transition
point over temperature, with or without external adjustment.

Bipolar Offset

Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an
analog value

1

offset error and temperature coefficient specify the initial
deviation and maximum change in the error over tempera­ture.

Full Scale Calibration Error

The last transition (from 1111 1111 1110 to 1111 1111

1111) should occur for an analog value 1
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actual level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
shown in Figures 2 and 3. The full scale calibration error
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.

1

/2 LSB (1.22mV for 10V span) before

1

/2 LSB beyond the last code tran-

1

/2 LSB. For these grades, this means that an

1

/2 LSB above analog

/2 LSB below analog common. The bipolar

1

/2 LSB below the

6-961

HI-574A, HI-674A, HI-774

Temperature Coefficients

The temperature coefficients for full-scale calibration, unipo­lar offset, and bipolar offset specify the maximum change
from the initial (25oC) value to the value at T

MIN

or T

MAX

.

Power Supply Rejection

The standard specifications for the HI-X74A assume use of
+5.00V and ±15.00V or ±12.00V supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.

Code Width

A fundamental quantity for A/D converter specifications is
the code width. This is defined as the range of analog input
values for which a given digital output code will occur. The
nominal value of a code width is equivalent to 1 least signifi­cant bit (LSB) of the full scale range or 2.44mV out of 10V for
a 12-bit ADC.

Quantization Uncertainty

Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±

1

/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.

Left-justified Data

Power Supplies

Supply voltages to the HI-X74(A) (+15V, -15V and +5V) must
be “quiet” and well regulated. Voltage spikes on these lines can
affect the converter’s accuracy, causing several LSBs to flicker
when a constant input is applied. Digital noise and spikes from
a switching power supply are especially troublesome. If switch­ing supplies must be used, outputs should be carefully filtered
to assure “quiet” DC voltage at the converter terminals.

Further, a bypass capacitor pair on each supply voltage
terminal is necessary to counter the effect of variations in
supply current. Connect one pair from pin 1 to 15 (V

LOGIC

supply), one from pin 7 to 9 (VCC to Analog Common) and
one from pin 11 to 9 (V

to Analog Common). For each

EE

capacitor pair, a 10µF tantalum type in parallel with a 0.1µF
ceramic type is recommended.

Ground Connections

Pins 9 and 15 should be tied together at the package to
guarantee specified performance for the converter. In
addition, a wide PC trace should run directly from pin 9 to
(usually) +15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some distance from
the system’s “single point” ground, make only these connec­tions to pins 9 and 15: Tie them together at the package, and
back to the system ground with a single path. This path
should have low resistance. (Code dependent currents flow in
the V

, VEE and V

CC

terminals, but not through the

LOGIC

HI-X74(A)’s Analog Common or Digital Common).

The data format used in the HI-X74(A) is left-justified. This
means that the data represents the analog input as a frac­tion of full-scale, ranging from 0 to . This implies a
binary point to the left of the MSB.

4095
4096

Applying the HI-X74(A)

For each application of this converter, the ground
connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must be
optimized to assure maximum performance. These areas
are reviewed in the following sections, along with basic oper­ating modes and calibration requirements.

Physical Mounting and Layout Considerations
Layout

Unwanted, parasitic circuit components, (L, R, and C) can
make 12-bit accuracy impossible, even with a perfect A/D
converter. The best policy is to eliminate or minimize these
parasitics through proper circuit layout, rather than try to
quantify their effects.

The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-to-point
wiring on vector board, will have an unpredictable effect on
accuracy.

In general, sensitive analog signals should be routed between
ground traces and kept well away from digital lines. If analog
and digital lines must cross, they should do so at right angles.

Analog Signal Source

HI-574A and HI-674A

The device chosen to drive the HI-X74A analog input will see a
nominal load of 5kΩ (10V range) or 10kΩ (20V range).
However, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in cur­rent at the analog input. Thus, the signal source must maintain
its output voltage while furnishing these step changes in load
current, which occur at 1.6µs and 950ns intervals for the
HI-574A and HI-674A, respectively. This requires low output
impedance and fast settling by the signal source.

The output impedance of an op amp, for example, has an open
loop value which, in a closed loop, is divided by the loop gain
available at a frequency of interest. The amplifier should have
acceptable loop gain at 600KHz for use with the HI-X74A. To
check whether the output properties of a signal source are
suitable, monitor the HI-X74A’ s input (pin 13 or 14) with an oscil­loscope while a conversion is in progress. Each of the twelve
disturbances should subside in 1µs or less for the HI-574A and
500ns or less for the HI-674A. (The comparator decision is
made about 1.5µs and 850ns after each code change from the
SAR for the HI-574A and HI-674A, respectiv ely.)

If the application calls for a Sample/Hold to precede the
converter, it should be noted that not all Sample/Holds are
compatible with the HI-574A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance. A simpler solution is to use the
Intersil HA-5320 Sample/Hold, which was designed for use
with the HI-574A.

6-962

HI-574A, HI-674A, HI-774

HI-774

The device driving the HI-774 analog input will see a nominal
load of 5kΩ (10V range) or 10kΩ (20V range). However, the
other end of these input resistors may change as much as
±400mV with each bit decision. These input disturbances
are caused by the internal DAC changing codes which
causes a glitch on the summing junction. This creates abrupt
changes in current at the analog input causing a “kick back”
glitch from the input. Because the algorithm starts with the
MSB, the first glitches will be the largest and get smaller as
the conversion proceeds. These glitches can occur at 350ns
intervals so an op amp with a low output impedance and fast
settling is desirable. Ultimately the input must settle to within
the window of Figure 1 at the bit decision points in order to
achieve 12-bit accuracy.

The HI-774 differs from the most high-speed successive
approximation type ADC’s in that it does not require a high
performance buffer or sample and hold. With error correction
the input can settle while the conversion is underway, but
only during the first 4.8µs. The input must be within 10.76%
of the final value when the MSB decision is made. This
occurs approximately 650ns after the conversion has been
initiated. Digital error correction also loosens the bandwidth
requirements of the buffer or sample and hold. As long as
the input “kick back” disturbances settle within the window of
Figure 1 the device will remain accurate. The combined
effect of settling and the “kick back” disturbances must
remain in the Figure 1 window.

If the design is being optimized for speed, the input device
should have closed loop bandwidth to 3MHz, and a low out­put impedance (calculated by dividing the open loop output
resistance by the open loop gain). If the application requires
a high speed sample and hold the Intersil HA-5330 or
HA-5320 are recommended.

In any design the input (pin 13 or 14) should be checked
during a conversion to make sure that the input stays within
the correctable window of Figure 1.

Digital Error Correction

HI-774

The HI-774 features the smart successive approximation
register (SSAR) which includes digital error correction. This
has the advantage of allowing the initial input to vary within a
+31 to -32 LSB window about the final value. The input can
move during the first 4.8µs, after which it must remain stable
within ±
before the input has settled completely; however, it must be
within the window as described in Figure 1.

The conversion cycle starts by making the first 8-bit decisions
very quickly, allowing the inter nal DAC to settle only to 8-bit
accuracy. Then the converter goes through two error correc­tion cycles. At this point the input must be stable within ±
LSB. These cycles correct the 8-bit word to 12-bit accuracy for
any errors made (up to +16 or -32 LSBs). This is up one count
or down two counts at 8-bit resolution. The converter then
continues to make the 4 LSB decisions, settling out to 12-bit
accuracy. The last four bits can adjust the code in the positive

1

/2 LSB. With this feature a conversion can start

1

direction by up to 15 LSBs. This results in a total correction
range of +31 to -32 LSBs. When an 8-bit conversion is per­formed, the input must settle to within ±

1

/2 LSB at 8-bit resolu-

tion (which equals ±8 LSBs at 12-bit resolution).
With the HI-774 a conversion can be initiated before the

input has completely settled, as long as it meets the con­straints of the Figure 1 window. This allows the user to start
conversion up to 4.8µs earlier than with a typical analog to
digital converter. A typical successive approximation type
ADC must have a constant input during a conversion
because once a bit decision is made it is locked in and can­not change.

32

8-BIT CONVERSION

16

BIT DECISION POINTS

8
0

-8

-16

-31

OFFSET

100K

100K

100Ω

0V TO +10V

0V TO +20V

MSB BIT DECISION

~ 650ns

1234567 8

TIME (µs)

R1

+15V

GAIN

R2

100Ω

ALLOWABLE INPUT CHANGE

(LSBs AT 12-BIT RESOLUTION)

CONVERSION

INITIATED

FIGURE 1. HI-774 ERROR CORRECTION WINDOW vs TIME

-15V

ANALOG

INPUTS

/

2

~ 4.8µs

12-BIT CONVERSION

2 12/

8

CS

3

4A

O

5R/C

6CE

10 REF IN

8 REF OUT

12 BIP OFF

13 10V

IN

14 20V

9 ANA

COM

۠

IN

CONVERSION

1

/2 LSB

±

LAST BIT

DECISION

(12-BIT)

STS 28

HIGH BITS

24-27

MIDDLE BITS

20-23

LOW BITS

16-19

+5V 1

+15V 7

-15V 11

DIG COM 15

†When driving the 20V (pin 14) input, minimize capacitance on pin 13.

FIGURE 2. UNIPOLAR CONNECTIONS

END OF

(12 BIT)

6-963

ANALOG

INPUTS

±5V

±10V

R2

R1

GAIN

100Ω

100Ω

OFFSET

2 12/

8

CS

3

4A

O

5R/C

6CE

10 REF IN

8 REF OUT

12 BIP OFF

13 10V

IN

14 20V

†

IN

9 ANA

COM

HI-574A, HI-674A, HI-774

adjustment is complete. Therefore, calibration is performed

STS 28

HIGH BITS

24-27

MIDDLE BITS

20-23

LOW BITS

16-19

+5V 1

+15V 7

-15V 11

DIG COM 15

in terms of the observable code changes instead of the
midpoint between code changes.

For example, midpoint of the first LSB increment should be
positioned at the origin, with an output code of all 0’s. To do
this, apply an input of +
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between
0000 0000 0000 and 0000 0000 0001.

Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is 1
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.

Bipolar Connections and Calibration

Refer to Figure 3. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiome­ters R1 and R2 (see Note). If this isn’t required, either or
both pots may be replaced by a 50Ω, 1% metal film resistor.

1

/2 LSB (+1.22mV for the 10V range;

1

/2 LSBs below the nominal full scale (+9.9963V for

†When driving the 20V (pin 14) input, minimize capacitance on pin 13.

FIGURE 3. BIPOLAR CONNECTIONS

Range Connections and Calibration Procedures

The HI-X74(A) is a “complete” A/D converter, meaning it is
fully operational with addition of the power supply voltages, a
Start Convert signal, and a few external components as
shown in Figure 2 and Figure 3. Nothing more is required for
most applications.

Whether controlled by a processor or operating in the stand­alone mode, the HI-X74(A) offers f our standard input ranges:
0V to +10V, 0V to +20V,±5V and ±10V. The maximum errors
for gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below . Power supply and ground connections have been dis­cussed in an earlier section.

Unipolar Connections and Calibration

Refer to Figure 2. The resistors shown (see Note) are for
calibration of offset and gain. If this is not required, replace
R2 with a 50Ω, 1% metal film resistor and remove the net­work on pin 12. Connect pin 12 to pin 9. Then, connect the
analog signal to pin 13 for the 0V to 10V range, or to pin 14
for the 0V to 20V range. Inputs to +20V (5V over the power
supply) are no problem - the converter operates normally.

Calibration consists of adjusting the converter’s most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is setting the output with respect to the mid­point of an increment of analog input, as denoted by two
adjacent code changes. Nominal value of an increment is
one LSB. However, this approach is impractical because
nothing “happens” at a midpoint to indicate that an

Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is sim­ilar to that for the unipolar ranges as discussed above. First
apply a DC input voltage

1

/2 LSB above negative full scale
(i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V
range). Adjust the offset potentiometer R1 for flick er between
output codes 0000 0000 0000 and 0000 0000 0001. Next,
apply a DC input voltage 1

1

/2 LSBs below positive full scale
(+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110 and 1111 1111 1111.

NOTE: The 100Ω potentiometer R2 provides Gain Adjust f or the 10V
and 20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 by a 50Ω, 1% metal film resistor. Then, to pro­vide Gain Adjust for the 10.24V range, add a 200Ω potentiometer in
series with pin 13. For the 20.48V range, add a 500Ω potentiometer
in series with pin 14.

Controlling the HI-X74(A)

The HI-X74(A) includes logic for direct interface to most
microprocessor systems. The processor may take full con­trol of each conversion, or the converter may operate in the
“stand-alone” mode, controlled only by the R/
control consists of selecting an 8-bit or 12-bit conversion
cycle, initiating the conversion, and reading the output data
when ready-choosing either 12 bits at once or 8 followed b y
4, in a left-justified format. The five control inputs are all
TTL/CMOS-compatible: (12/

8, CS, AO, R/C and CE). Table
1 illustrates the use of these inputs in controlling the
converter’s operations. Also, a simplified schematic of the
internal control logic is shown in Figure 7.

C input. Full

6-964

HI-574A, HI-674A, HI-774

“Stand-Alone Operation”

The simplest control interface calls for a singe control line
connected to R/
A

are wired low, and the output data appears in words of

O

C. Also, CE and 12/8 are wired high,CS and

12 bits each.
The R/

C signal may have any duty cycle within (and
including) the extremes shown in Figures 8 and 9. In gen­eral, data may be read when R/

C is high unless STS is also
high, indicating a conversion is in progress. Timing parame­ters particular to this mode of operation are listed below
under “Stand-Alone Mode Timing”.

HI-574A STAND-ALONE MODE TIMING

SYMBOL PARAMETER MIN TYP MAX UNITS

t

t

t
t

Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.

Low R/C Pulse Width 50 - - ns

HRL

t

STS Delay from R/C - - 200 ns

DS

Data Valid after R/C L ow 25 - - ns

HDR

t

STS Delay after Data V alid 300 - 1200 ns

HS

High R/C Pulse Width 150 - - ns

HRH

Data Access Time - - 150 ns

DDR

HI-674A STAND-ALONE MODE TIMING

Conversion Length

A Convert Start transition (see Table 1) latches the state of
A

, which determines whether the conversion continues for

O

12 bits (A

low) or stops with 8 bits (AO high). If all 12 bits are

O

read following an 8-bit conversion, the last three LSBs will
read ZERO and DB3 will read ONE. A

is latched because it

O

is also involved in enabling the output buffers (see “Reading
the Output Data”). No other control inputs are latched.

TABLE 1. TRUTH TABLE FOR HI-X74(A) CONTROL INPUTS

CE CS R/C 12/8A

0XXXXNone
X 1 X X X None

↑ 0 0 X 0 Initiate 12-bit conversion
↑ 0 0 X 1 Initiate 8-bit conversion

1 ↓ 0 X 0 Initiate 12-bit conversion
1 ↓ 0 X 1 Initiate 8-bit conversion
10↓ X 0 Initiate 12-bit conversion
10↓ X 1 Initiate 8-bit conversion
1011XEnable 12-bit Output
10100Enable 8 MSBs Only
10101Enable 4 LSBs Plus 4 Trailing

O

Zeroes

OPERATION

SYMBOL PARAMETER MIN TYP MAX UNITS

t

t

t
t

Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.

SYMBOL PARAMETER MIN TYP MAX UNITS

t

t

t
t

Low R/C Pulse Width 50 - - ns

HRL

t

STS Delay from R/C - - 200 ns

DS

Data Valid after R/C L ow 25 - - ns

HDR

t

STS Delay after Data V alid 25 - 850 ns

HS

High R/C Pulse Width 150 - - ns

HRH

Data Access Time - - 150 ns

DDR

HI-774 STAND-ALONE MODE TIMING

Low R/C Pulse Width 50 - - ns

HRL

t

STS Delay from R/C - - 200 ns

DS

Data Valid after R/C L ow 20 - - ns

HDR

t

STS Delay after Data V alid - - 850 ns

HS

High R/C Pulse Width 150 - - ns

HRH

Data Access Time - - 150 ns

DDR

Conversion Start

A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE,

CS or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-774 Timing Specifications, Convert Mode.

This variety of HI-X74(A) control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 4.

The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or reinitiate a conversion while
STS is high.

Reading the Output Data

The output data buffers remain in a high impedance state
until four conditions are met: R/

C high, STS low , CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/

8 and AO. Timing constraints are

illustrated in Figure 5.

6-965

HI-574A, HI-674A, HI-774

The 12/
though it is fully TTL/CMOS-compatible. With 12/

8 input will be tied high or low in most applications,

8 high, all
12 output lines become active simultaneously, for interface to
a 12-bit or 16-bit data bus. The A

With 12/

8 low, the output is organized in two 8-bit bytes,
selected one at a time by A
to be connected as shown in Figure 6. A

input is ignored.

O

. This allows an 8-bit data bus

O

is usually tied to

O

the least significant bit of the address bus, for storing the
HI-X74(A) output in two consecutive memory locations.
(With A

low, the 8 MSBs only are enabled. With AO high, 4

O

MSBs are disabled, bits 4 through 7 are forced low, and the 4
LSBs are enabled). This two byte format is considered “left
justified data,” for which a decimal (or binary!) point is
assumed to the left of byte 1:

BYTE 1 BYTE 2

XXXXXXXX XXXX0000

•

MSB LSB

Further, A

may be toggled at any time without damage to

O

the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 6 will never be enabled at the
same time.

A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (t

DD

+ tHS)

before STS goes low. See Figure 5.

CE

CS

R/

A

STS

DB11-DB0

t

SSR

C

t

O

SRR

t

SAR

HIGH IMPEDANCE

t

DD

t

HSR

t

HRR

t

HAR

t

HS

See HI-774 Timing Specifications for more information.

FIGURE 5. READ CYCLE TIMING

A

O

ADDRESS BUS

DAT A

VALID

t

HD

t

HL

t

CE

CS

R/

A

STS

DB11-DB0

t

SSC

t

SRC

C

t

t

SAC

HRC

t

HAC

t

DSC

HIGH IMPEDANCE

O

HEC

t

HSC

See HI-774 Timing Specifications for more information.

FIGURE 4. CONVERT START TIMING

1
2

8

DB11 (MSB)

12/
3
4

A

O

5
6
7
8
9

t

C

10
11
12
13
14

HI-774

DB0 (LSB)

STS

DIG.

COM.

28
27
26
25
24
23
22
21
20
19
18
17
16
15

DAT A
BUS

FIGURE 6. INTERFACE TO AN 8-BIT DATA BUS

6-966

HI-574A, HI-674A, HI-774

NIBBLE B ZERO
OVERRIDE

INPUT BUFFERS

8

12/

CS

A

O

R/

C

CE

CK

Q

D

Q

AO LATCH

EOC9

EOC13

READ CONTROL

POWER UP

RESET

FIGURE 7. HI-774 CONTROL LOGIC

t

HRL

CONVERT
CONTROL

CURRENT

CONTROLLED

OSCILLATOR

NIBBLE A, B

NIBBLE C

STATUS

STROBE
CLOCK

RESET

R/C

t

DS

STS

DB11-DB0

DAT A

VALID

t

HDR

t

C

FIGURE 8. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION

R/

C

STS

DB11-DB0

t

DDR

t

HRH

DAT A

VALID

t

HDR

t

DS

t

C

HIGH-ZHIGH-Z

t

HS

DAT A

VALID

FIGURE 9. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z

6-967

Die Characteristics

HI-574A, HI-674A, HI-774

DIE DIMENSIONS:

Analog: 3070mm x 4610mm
Digital: 1900mm x 4510mm

METALLIZATION:

Digital Type: Nitrox
Thickness: 10k

Å ±2kÅ

Metal 1: AlSiCu
Thickness: 8k

Å ±1kÅ

Metal 2: AlSiCu
Thickness: 16k

Å ±2kÅ

Analog Type: Al
Thickness: 16k

Å ±2kÅ

Metallization Mask Layout

O

R/C

CE

V

A

CC

CS

PASSIVATION:

Type: Nitride Over Silox
Nitride Thickness: 3.5k
Silox Thickness: 12kű1.5kÅ

WORST CASE CURRENT DENSITY:

1.3 x 10

HI-574A, HI-674A, HI-774

5

A/cm

Å ±0.5kÅ

2

LOGIC

LOGIC

V

STS

12/8

V

DB11

DB10

DB9

V

REFOUT

ANALOG

COMMON

ANALOG

COMMON

ANALOG

COMMON

V

REFIN

V

EE

10VIN20V

OFFSET

BIPOLAR

DB8

DB7

DB6

DB5

DB4

DB3

DB2

IN

DIGITAL

COMMON

DB0

DB1

6-968

HI-574A, HI-674A, HI-774

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

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Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

6-969

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Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]