Datasheet HI-539 Datasheet (Intersil Corporation)

HI-539

Data Sheet July 1999

Precision, 4-Channel, Low-Level,
Differential Multiplexer

The Intersil HI-539 is a monolithic, 4-Channel, differential
multiplexer. Two digital inputs are provided for channel
selection, plus an Enable input to disconnect all channels.

Performance is guaranteed for each channel over the
voltage range ±10V, but is optimized for low level differential
signals. Leakage current, for example, which varies slightly
with input voltage, has its distribution centered at zero input
volts.

In most monolithic multiplexers, the net differential offset due
to thermal effects becomes significant for low level signals.
This problem is minimized in the HI-539 by symmetrical
placement of critical circuitry with respect to the few heat
producing devices.

Supply voltages are ±15V and power consumption is only

2.5mW.

Ordering Information

TEMP.

PART NUMBER

RANGE (oC) PACKAGE

HI1-0539-5 0 to 75 16 Ld CERDIP F16.3
HI1-0539-8 -55 to 125 16 Ld CERDIP F16.3
HI3-0539-5 0 to 75 16 Ld PDIP E16.3
HI4P0539-5 0 to 75 20 Ld PLCC N20.35

PKG.

NO.

File Number

3149.2

Features

• Differential Performance, Typical:

-Low∆r

-Low∆I

, 125oC . . . . . . . . . . . . . . . . . . . . . . . . . .5.5Ω

ON

, 125oC. . . . . . . . . . . . . . . . . . . . . . . 0.6nA

D(ON)

-Low∆ Charge Injection . . . . . . . . . . . . . . . . . . . . 0.1pC

- Low Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . -124dB

• Settling Time, ±0.01% . . . . . . . . . . . . . . . . . . . . . . .900ns

• Wide Supply Range . . . . . . . . . . . . . . . . . . . ±5V to ±18V

• Break-Before-Make Switching

• No Latch-Up

Applications

• Low Level Data Acquisition

• Precision Instrumentation

• Test Systems

TRUTH TABLE

ON CHANNEL TO

EN A

1

L X X None None
HLL1A1B
HLH2A2B
HHL3A3B
H H H 4A 4B

A

0

OUT A OUT B

Pinouts

A

EN

IN 1A
IN 2A
IN 3A
IN 4A

OUT A

(CERDIP, PDIP)

TOP VIEW

1

0

2
3

V-

4
5
6
7
8

HI-539

1

16
15
14
13
12
11
10

9

A

1

GND
V+
IN 1B
IN 2B
IN 3B
IN 4B
OUT B

HI-539

(PLCC)

TOP VIEW

0

A

EN

4

V-

IN 1A

5
6

NC

IN 2A

7

IN 3A

8

9

10 11 12 13

IN 4A

OUT ANCOUT B

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

1

A

NC

GND

193 2 201

18

V+

17

IN 1B

16

NC

15

IN 2B
IN 3B

14

IN 4B

| Copyright © Intersil Corporation 1999

HI-539

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V

V+ or V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V

Analog Signal (VIN, V

). . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+

OUT

Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . . . V- to V+

Analog Current (IN or OUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Operating Conditions

Temperature Range

HI-539-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

HI-539-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

CERDIP Package. . . . . . . . . . . . . . . . . 85 32

PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A

PLCC Package. . . . . . . . . . . . . . . . . . . 80 N/A

Maximum Junction Temperature

Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(PLCC - Lead Tips Only)

Electrical Specifications Supplies = ±15V, V

= 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V,

EN

Unless Otherwise Specified

-8 -5
UNITSMIN TYP MAX MIN TYP MAX

PARAMETER

TEST

CONDITIONS

TEMP

(oC)

DYNAMIC CHARACTERISTICS

Access Time, t

A

25 - 250 750 - 250 750 ns

Full - - 1,000 - - 1,000 ns

Break-Before-Make Delay, t

OPEN

25 30 85 - 30 85 - ns

Full 30 - - 30 - - ns

Enable Delay (ON), t

ON(EN)

25 - 250 750 - 250 750 ns

Full - - 1,000 - - 1,000 ns

Enable Delay (OFF), t

OFF(EN)

25 - 160 650 - 160 650 ns

Full - - 900 - - 900 ns
Settling Time To 0.01% 25 - 0.9 - - 0.9 - µs
Charge Injection (Output) Full - 3 - - 3 - pC
∆ Charge Injection (Output) Full - 0.1 - - 0.1 - pC
Charge Injection (Input) Full - 10 - - 10 - pC
Differential Crosstalk Note 4 25 - -124 - - -124 - dB
Single Ended Crosstalk Note 4 25 - -100 - - -100 - dB
Channel Input Capacitance,

C

S(OFF)

Channel Output Capacitance,
C

D(OFF)

Channel On Output Capacitance,
C

D(ON)

Input to Output Capacitance,
C

DS(OFF)

Digital Input Capacitance, C

A

Note 5 Full - 0.08 - - 0.08 - pF

Full - 5 - - 5 - pF

Full - 7 - - 7 - pF

Full - 17 - - 17 - pF

Full - 3 - - 3 - pF

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, V
Input High Threshold, V

AL

AH

Input Leakage Current (High), I
Input Leakage Current (Low), I

AH

AL

Full - - 0.8 - - 0.8 V

Full 4.0 - - 4.0 - - V

Full - - 1 - - 1 µA

Full - - 1 - - 1 µA

2

HI-539

Electrical Specifications Supplies = ±15V, V

= 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V,

EN

Unless Otherwise Specified (Continued)

-8 -5
UNITSMIN TYP MAX MIN TYP MAX

PARAMETER

TEST

CONDITIONS

TEMP

(oC)

ANALOG CHANNEL CHARACTERISTICS

Analog Signal Range, V
On Resistance, r

ON

IN

VIN = 0V 25 - 650 850 - 650 850 Ω

Full -10 - +10 -10 - +10 V

Full - 950 1.3K - 800 1K Ω

VlN = ±10V 25 - 700 900 - 700 900 Ω

Full - 1.1K 1.4K - 900 1.1K Ω

∆r

(Side A-Side B) VIN = 0V 25 - 4.0 24 - 4.0 24 Ω

ON,

Full - 4.75 28 - 4.0 24 Ω

VlN = ±10V 25 - 4.5 27 - 4.5 27 Ω

Full - 5.5 33 - 4.5 27 Ω

Off Input Leakage Current, I

∆I

(Side A-Side B) Condition 0V 25 - 3 - - 3 - pA

S(OFF),

S(OFF)

Condition 0V
(Note 2)

Condition ±10V
(Note 2)

25 -30- -30-pA

Full - 2 10 - 0.2 1 nA

25 - 100 - - 100 - pA

Full - 5 25 - 0.5 2.5 nA

Full - 0.2 2 - 0.02 0.2 nA

Condition ±10V 25 - 10 - - 10 - pA

Full - 0.5 5 - 0.05 0.5 nA

Off Output Leakage Current,
I

D(OFF)

∆I

(Side A-Side B) Condition 0V 25 - 3 - - 3 - pA

D(OFF),

Condition 0V
(Note 2)

Condition ±10V
(Note 2)

25 -30- -30-pA

Full - 2 10 - 0.2 1 nA

25 - 100 - - 100 - pA

Full - 5 25 - 0.5 2.5 nA

Full - 0.2 2 - 0.02 0.2 nA

Condition ±10V 25 - 10 - - 10 - pA

Full - 0.5 5 - 0.05 0.5 nA

On Channel Leakage Current, I

∆I

(Side A-Side B) Condition 0V 25 - 10 - - 10 - pA

D(ON),

D(ON)

Condition 0V
(Note 2)

Condition ±10V
(Note 2)

25 -50- -50-pA

Full - 5 25 - 0.5 2.5 nA

25 - 150 - - 150 - pA

Full - 6 40 - 0.8 4.0 nA

Full - 0.5 5 - 0.05 0.5 nA

Condition ±10V 25 - 30 - - 30 - pA

Full - 0.6 6 - 0.08 0.8 nA

Differential Offset Voltage, ∆V

OS

Note 3 25 - 0.02 - - 0.02 - µV

Full - 0.70 - - 0.08 - µV

POWER SUPPLY CHARACTERISTICS

Power Dissipation, P

D

25 - 2.3 - - 2.3 - mW

Full - - 45 - - 45 mW

Current, l+ 25 - 0.150 - - 0.150 - mA

Full - - 2.0 - - 2.0 mA

3

HI-539

Electrical Specifications Supplies = ±15V, V

= 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V,

EN

Unless Otherwise Specified (Continued)

-8 -5
UNITSMIN TYP MAX MIN TYP MAX

PARAMETER

TEST

CONDITIONS

TEMP

(oC)

Current, l- 25 - 0.001 - - 0.001 - mA

Full - - 1.0 - - 1.0 mA

Supply Voltage Range Full ±5 ±15 ±18 ±5 ±15 ±18 V

NOTES:

2. See Figures 2B, 2C, 2D. The condition ±10V means:
l

S(OFF)

and I

D(OFF)

:
(VS = +10V, VD = -10V), then
(VS = -10V, VD = +10V)
I

: (+10V, then -10V)

D(ON)

3. ∆VOS(Exclusive of thermocouple effects) = rON∆I

4. VlN = 1kHz, 15V

on all but the selected channel. See Figure 7.

P-P

D(ON)

+ I

D(ON)∆rON

. See Applications section for discussion of additional VOS error.

5. Calculated from typical Single-Ended Crosstalk performance.

T est Cir cuits and Waveforms

100µA

V

2

Unless Otherwise Specified TA = 25oC, V+ = +15V, V - = -15V, VAH = 4V and VAL = 0.8V

VIN = 0V

800

700

OUTIN

V

V

IN

HI-539

rON =

2

100µA

600

ON RESISTANCE (Ω)

500

-25 0 25 50 75 100 125

-50
TEMPERATURE (

o

C)

FIGURE 1A. TEST CIRCUIT FIGURE 1B. ON RESISTANCE vs TEMPERATURE

900

125oC

800

700

600

ON RESISTANCE (Ω)

500

400

-12

-10 -8 -6 -4 -2 0 2 4 8 10612

25oC

-55oC

ANALOG INPUT (V)

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

ON RESISTANCE (kΩ)

0.9

0.8

0.7

0.6

0.5
5 7 9 11 13 15 17

SUPPLY VOLTAGE (±V)

VIN = 0V

FIGURE 1C. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1D. ON RESISTANCE vs SUPPLY VOLTAGE

FIGURE 1. ON RESISTANCE

4

HI-539

T est Cir cuits and Waveforms

10

I

D(ON)

1

LEAKAGE CURRENT (nA)

25

50 75 100 125

I

D(OFF)

TEMPERATURE (

Unless Otherwise Specified TA = 25oC, V+ = +15V, V - = -15V, VAH = 4V and VAL = 0.8V (Continued)

= I

S(OFF)

o

C)

±10V

FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. I

†

HI-539

OUT A

I

A

S(OFF)

±10V

±

10V

A

0

A

1

EN

0.8V

±

10V

HI-539†

EN

A

0

A

1

† Similar Connection For Side “B”

TEST CIRCUIT (NOTE 6)

D(OFF)

HI-539†

A

0

EN

A

1

OUT A

OUT A

4V

0.8V

I

A

D(OFF)

±

10V

A

I

D(ON)

±10V

†Similar Connection For Side “B”

FIGURE 2C. I

TEST CIRCUIT (NOTE 6) FIGURE 2D. I

S(OFF)

†Similar Connection For Side “B”

TEST CIRCUIT (NOTE 6)

D(ON)

NOTE:

6. Three measurements = ±10V, 10V, and 0V.

±

FIGURE 2. LEAKAGE CURRENT

+15V/+10V

14

12

10

8

6

4

I+ SUPPLY CURRENT (mA)

2

0

100Hz

1kHz 10kHz 100kHz 1MHz 3MHz 10MHz

FUNCTIONAL LIMIT

V

SUPPLY

V

SUPPLY

TOGGLE FREQUENCY

= ±15V

= ±10V

50Ω

V

A

HIGH = 4.0V
LOW = 0V

V

A

50% DUTY CYCLE

A

1

HI-539

A

0

5V

EN

GND

†Similar Connection For Side “B”

A

V+

IN 1A

†

IN 2A

IN 3A

IN 4A

OUT A

V-

A

+I

-I

-15V/-10V

FIGURE 3A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 3B. TEST CIRCUIT

FIGURE 3. DYNAMIC SUPPLY CURRENT

SUPPLY

SUPPLY

+10V/+5V

-10V/-5V

10MΩ

14pF

5

HI-539

T est Cir cuits and Waveforms

320

300

280

260

240

ACCESS TIME (ns)

220

200

3

456789101112131415

LOGIC LEVEL (HIGH) (V)

Unless Otherwise Specified TA = 25oC, V+ = +15V, V - = -15V, VAH = 4V and VAL = 0.8V (Continued)

A

1

A

0

50Ω

V

A

5V

EN

HI-539

GND

FIGURE 4A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 4B. TEST CIRCUIT

= 4V

V

AH

50%

ADDRESS
DRIVE (V

)

A

0V

VA INPUT
2V/DIV.

S1 ON

+15V

V+

IN 1A

IN 2A,

IN 3A

IN 4A

OUT A

V-

-15V

±

10V

±10V

kΩ

50

10

pF

+10V

10%

t

A

OUTPUT

-10V

200ns/DIV.

OUTPUT
5V/DIV.

S4 ON

FIGURE 4C. MEASUREMENT POINTS FIGURE 4D. WAVEFORMS

FIGURE 4. ACCESS TIME

+15V

0V

VAH = 4V

50% 50%

t

ADDRESS
DRIVE (V

OPEN

)

A

OUTPUT

HI-539†

A

1

A

0

EN

5V

50ΩV

A

IN 2, IN 3A

GND

V+

IN 1A

IN 4A

OUT A

V-

-15V

†Similar connection for side “B”

700

+5V

V

OUT

Ω

12.5pF

FIGURE 5A. MEASUREMENT POINTS FIGURE 5B. TEST CIRCUIT

6

HI-539

T est Cir cuits and Waveforms

VAH = 4V

Unless Otherwise Specified TA = 25oC, V+ = +15V, V - = -15V, VAH = 4V and VAL = 0.8V (Continued)

VA INPUT
2V/DIV.

S1 ON

100ns/DIV.

S4 ON

OUTPUT
1V/DIV.

FIGURE 5C. WAVEFORMS

FIGURE 5. BREAK-BEFORE-MAKE DELAY

+15V

HI-539

V+

†

IN 1A

+10V

50%

90%

t

ON(EN)

50% ENABLE DRIVE (V

0V

OUTPUT

10%

0V

t

OFF(EN)

)

A

V

A

50

Ω

A
A

EN

1

0

GND

IN 2A THRU

†Similar connection for side “B”

FIGURE 6A. MEASUREMENT POINTS FIGURE 6B. TEST CIRCUIT

ENABLE

DRIVE

2V/DIV.

DISABLED

ENABLED

(S1 ON)

OUTPUT

2V/DIV.

IN 4A

OUT A

V-

-15V

700

V

OUT

Ω

12.5pF

100ns/DIV.

FIGURE 6C. WAVEFORMS

FIGURE 6. ENABLE DELAYS

7

HI-539

T est Cir cuits and Waveforms

HI-539

1kHz,
15V

P-P

350Ω

†AD606 or BB3630, for Example

FIGURE 7A. SINGLE-ENDED CROSSTALK TEST CIRCUIT FIGURE 7B. DIFFERENTIAL CROSSTALK TEST CIRCUIT

Application Information

Unless Otherwise Specified TA = 25oC, V+ = +15V, V - = -15V, VAH = 4V and VAL = 0.8V (Continued)

INSTRUMENTATION

AMPLIFIER

G = 1000

+

†

-

1kHz,
15V

HI-539

350Ω

350Ω

P-P

INSTRUMENTATION

AMPLIFIER

G = 1000

+

-

†AD606 or BB3630, for example

FIGURE 7. CROSSTALK

Coaxial cable is not suitable for lo w le vel signals because the
two conductors (center and shield) are unbalanced. Also,

General

The Hl-539 accepts inputs in the range -15V to +15V, with
performance guaranteed over the ±10V range. At these
higher levelsof analog inputvoltage it is comparable to the Hl­509, and is plug-in compatiblewith that device (as wellas the
Hl-509A). Howev er, as mentioned earlier, the Hl-539 was
designed to introduce minimum error when switchinglow level
inputs.

Special care is required in working with these low level
signals. The main concern with signals below 100mV is that
noise, offset voltage, and other aberrations can represent a
large percentage error. A shielded differential signal path is
essential to maintain a noise level below 50µV

RMS

.

Low Level Signal Transmission

The transmission cable carrying the transducer signal is critical
in a low level system. It should be as short as practical and
rigidly supported. Signal conductors should be tightly twisted
for minimum enclosed area to guard against pickup of
electromagnetic interference, and the twisted pair should be
shielded against capacitively coupled (electrostatic)
interference. A braided wire shield ma y be satisfactory, but a
lapped foil shield is better since it allows only
leakage capacitance to ground per foot. A ke y requirement f or
the transmission cable is that it presents a balanced line to
sources of noise interference. This means an equal series

1

/10 as much

ground loops are produced if the shield is grounded at both
ends by standard BNC connectors. If coax must be used, carry
the signal on the center conductors of two equal-length cables
whose shields are terminated only at the transducer end. As a
general rule, terminate (ground) the shield at one end only ,
preferably at the end with greatest noise interference. This is
usually the transducer end for both high and low le v el signals .

Watch Small∆V Errors

Printed circuit traces and short lengths of wire can add
substantial error to a signal even after it has traveled
hundreds of feet and arrived on a circuit board. Here, the
small voltage drops due to current flow through connections
of a fewmilliohms must be considered, especially to meet an
accuracy requirement of 12 bits or more.

Table 1 is a useful collection of data for calculating theeffect
of these short connections. (Proximity to a ground plane will
lower the values of inductance.)

As an example, suppose the Hl-539 is feeding a 12-bit
converter system with an allowable error of ±
(±1.22mV). lf the interface logic draws 100mA from the 5V
supply, this current will produce 1.28mV across 6 inches of
#24 wire; more than the error budget. Obviously, this digital
current must not be routed through any portion of theanalog
ground return network.

1

/2 LSB

impedance in each conductor plus an equally distributed
impedance from each conductor to ground. The result should
be signals equal in magnitude but opposite in phase at any
transverse plane. Noise will be coupled in phase to both
conductors, and may be rejected as common-mode voltage b y
a differential amplifier connected to the multiplexer output.

†

8

HI-539

TABLE 1.

EQUIVALENT WIDTH OF

P.C. CONDUCTOR

WIRE GAGE

18 0.47” 0.0064Ω 0.36µH 0.0064Ω 0.0235Ω
20 0.30” 0.0102Ω 0.37µH 0.0102Ω 0.0254Ω
22 0.19” 0.0161Ω 0.37µH 0.0161Ω 0.0288Ω
24 0.12” 0.0257Ω 0.40µH 0.0257Ω 0.0345Ω
26 0.075” 0.041Ω 0.42µH 0.041Ω 0.0488Ω
28 0.047” 0.066Ω 0.45µH 0.066Ω 0.0718Ω
30 0.029” 0.105Ω 0.49µH 0.105Ω 0.110Ω
32 0.018” 0.168Ω 0.53µH 0.168Ω 0.171Ω

(2 oz. Cu)

DC RESISTANCE

PER FOOT

INDUCTANCE PER

FOOT

IMPEDANCE PER FOOT

60Hz 10kHz

Provide Path For I

BIAS

The input bias current for any DC-coupled amplifier must
have an external path back to the amplifier’s power supply.
No such path exists in Figure 8A, and consequently the
amplifier output will remain in saturation.

A single large resistor (1MΩ to10MΩ) from eithersignal line
to powersupply common will provide the required path, but a
resistor on each line is necessary to preserve accuracy. A
single pair of these bias current resistors on the HI-539
output may be used if their loading effect can be tolerated
(each formsa voltage divider with r

). Otherwise,a resistor

ON

pair on each input channel of the multiplexer is required.
The use of bias current resistors is acceptable only if one is

confident that the sum of signal plus common-mode voltage
will remain within the input range of the multiplexer/amplifier
combination.

Another solution is to simply run a third wire from the low
side of the signal source, as in Figure 8B. This wire assures
a low common-mode voltage as well as providing the path
for bias currents. Making the connection near the multiplexer
will save wire, but it will also unbalance the line and reduce
the amplifier's common-mode rejection.

Differential Offset,∆V

OS

There are two major sources of ∆VOS. That part due to the
expression(r

ON∆lD(ON)+lD(ON)∆rON

) becomes significant
with increasing temperature, as shown in the Electrical
Specifications tables. The other source of offset is the
thermocouple effects due to dissimilar materials in the signal
path. These include silicon, aluminum, tin, nickel-iron and
(often) gold, just to exit the package.

For the thermocouple effects in the package alone, the
constraint on ∆V

may be stated in terms of a limit on the

OS

difference in temperature for package pins leading to any
channel of the Hl-539. For example, a difference of 0.13

o

C
produces a 5µV offset. Obviously, this ∆T effect can
dominate the ∆V

parameter at any temperature unless

OS

care is taken in mounting the Hl-539 package.
Temperature gradients across the Hl-539 package should be

held to a minimum in critical applications. Locate the Hl-539
far from heat producing components, with any air currents
flowing lengthwise across the package.

9

HI-539

“FLOATING”

SOURCE

HI-539

r

ON

r

ON

V+

+

-

V-

FIGURE 8A.

1M TO 10M

POWER SUPPLY
COMMON

HI-539

r

ON

r

ON

POWER SUPPLY
COMMON

V+

+

-

V-

NOTE: The amplifier in Figure 8A is unusable because its bias currents cannot return to the power supply. Figure 8B shows two alternative paths
for these bias currents: either a pair of resistors, or (better) a third wire from the low side of the signal source.

FIGURE 8B.

10

Die Characteristics

HI-539

DIE DIMENSIONS:

92 mils x 100 mils

METALLIZATION:

Type: AlCu
Thickness: 16k

Å ±2kÅ

SUBSTRATE POTENTIAL (NOTE):

-V

SUPPLY

NOTE: The substrate appears resistive to the -V
conductor at -V

SUPPLY

potential.

Metallization Mask Layout

V- EN A

PASSIVATION:

Type: Nitride Over Silox
Nitride Thickness: 3.5k

Å ±1kÅ

Silox Thickness: 12kű2.0kÅ

WORST CASE CURRENT DENSITY:

5

2.54 x 10

A/cm2 at 20mA

TRANSISTOR COUNT:

236

PROCESS:

CMOS-DI

terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a

SUPPLY

HI-539

A

0

1

GND V+

IN1A

IN2A

OUTB IN4BIN4A OUTAIN3A

IN1B

IN2B

IN3B

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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