Datasheet HI-3282PQT, HI-3282PQI, HI-3282PJT, HI-3282PJI, HI-3282CDT Datasheet (HOLT)

HI-3282

GENERALDESCRIPTION

TheHI-3282isasilicongateCMOSdeviceforinterfacing
theARINC429serialdatabustoa16-bitparalleldatabus.
Tworeceiversandanindependenttransmitterare
provided.Thereceiverinputcircuitryandlogicare
designedtomeettheARINC429specificationsforloading,
leveldetection,timing,andprotocol.Thetransmitter
sectionprovidestheARINC429communicationprotocol.
AdditionalinterfacecircuitrysuchastheHoltHI-8382orHI­8585arerequiredtotranslatethe5voltlogicoutputsto
ARINC429drivelevels.

The16-bitparalleldatabusexchangesthe32-bitARINC
da tawordintwostepswheneitherloadingthetransmitter
orinterrogatingthereceivers.Thedatabusinterfaceswith
CMOSandTTL.

Timingofallthecircuitrybeginswiththemasterclockinput,
CLK.ForARINC429applications,themasterclock
frequencyis1MHz.

Eachindependentreceivermonitorsthedatastreamwitha
samplingrate10timesthedatarate.Thesamplingrateis
softwareselectableateither1MHzor125KHz.Theresults
ofaparitycheckareavailableasthe32ndARINCbit.

FEATURES

!

ARINCspecification429compatible

!

CompatiblewithIndustry-standardalternate

Parts

!

Smallfootprint44PQFPpackageoption

!

16-Bitparalleldatabus

!

DirectreceiverinterfacetoARINCbus

!

Timingcontrol10timesthedatarate

!

Selectabledataclocks

!

Automatictransmitterdatatiming

!

Selftestmode

!

Parityfunctions

!

Lowpower,single5voltsupply

!

Industrial&fullmilitarytemperatureranges

ThetransmitterhasaFirstIn,FirstOut(FIFO)memoryto
store8ARINCwordsfortransmission.Thedatara teofthe
transmitterissoftwareselectablebydividingthemaster
clock,CLK,byeither10or80.Themasterclockisusedto
setthetimingoftheARINCtransmissionwithintherequired
resolution.

APPLICATIONS

!

Avionicsdatacommunication

!

Serialtoparallelconversion

!

Paralleltoserialconversion

N/C-1
D/R1
D/R2

SEL-4
EN1

EN2
BD15-7
BD14-8
BD13-9
BD12-10

BD11-11

33-N/C

-2

-3

-5

-6

HI-3282PQI

&

HI-3282PQT

32-N/C
31-X

CWSTR
30-ENTX
29-

429DO
28-429DO
27-TX/R
26-

PL2
25-

PL1
24-BD00
23-BD01

HOLTINTEGRATEDCIRCUITS

1(DS3282Rev.E)05/01

PINDESCRIPTION

SYMBOLFUNCTIONDESCRIPTION

VCCPOWER+5V±5%
429DI1(A)INPUTARINCreceiver1positiveinput
429DI1(B)INPUTARINCreceiver1negativeinput
429DI2(A)INPUTARINCreceiver2positiveinput
429DI2(B)INPUTARINCreceiver2negativeinput

D/R1
D/R2

SELINPUTReceiverdatabyteselection(0=BYTE1)(1=BYTE2)
EN1

EN2EN1
BD15I/ODataBus
BD14I/ODataBus
BD13I/ODataBus
BD12I/ODataBus
BD11I/ODataBus
BD10I/ODataBus
BD09I/ODataBus
BD08I/OData Bus
BD07I/ODataBus
BD06I/ODataBus

GNDPOWER0V
BD05I/ODataBus
BD04I/ODataBus
BD03I/ODataBus
BD02I/ODataBus
BD01I/ODataBus
BD00I/ODataBus

PL1
PL2PL1.

TX/ROUTPUTTransmitterreadyflag.GoeslowwhenARINCwordloadedintoFIFO.Goeshigh

429DOOUTPUT"ONES"dataoutputfromtransmitter.
429DO

ENTXINPUTEnableTransmission

CWSTR

CLKINPUTMasterClockinput

TXCLKOUTPUTTransmitterClockequaltoMasterClock(CLK),dividedbyeither10or80.

MR

DBCEN

OUTPUTReceiver1datareadyflag
OUTPUTReceiver2datareadyflag

INPUTDataBuscontrol,enablesreceiver1datatooutputs
INPUTDataBuscontrol,enablesreceiver2datatooutputsifishigh

INPUTLatchenableforbyte1enteredfromdatabustotransmitterFIFO.
INPUTLatchenableforbyte2enteredfromdatabustotransmitterFIFO.Mustfollow

OUTPUT"ZEROES"dataoutputfromtransmitter.

INPUTClockforcontrolwordregiste r

INPUTMasterReset,activelow
INPUTDatabitcontrolEnable.(Activelow,withinternalpulluptoVDD).

HI-3282

aftertransmissionandFIFOempty.

HOLTINTEGRATEDCIRCUITS

2

HI-3282

FUNCTIONALDESCRIPTION

CONTROLWORDREGISTER

TheHI-3282contains11dataflipflopswhoseDinputsarecon­nectedtothedatabusandclocksconnectedto.Each
flipflopprovidesoptionstotheuserasfollows:

DATA

BUSFUNCTIONCONTROLDESCRIPTION

PIN

BD04PARENEnablesparitybitinsertioninto

Transmitterdatabit32

Ifenabled,aninternalconnection

BDO5SELFTEST0=ENABLEismadepassing429DOand

429DO

RECEIVER1Ifenabled,ARINCbits9and,

BDO6DECODER1=ENABLE10mustmatchthenexttwo

IfReceiver1Decoderis

BDO7--enabled,theARINCbit9

IfReceiver1Decoderis

BDO8--enabled,theARINCbit10

RECEIVER2Ifenabled,ARINCbits9and

BDO9DECODER1=ENABLE10mustmatchthenexttwo

IfReceiver2Decoderis

BD10--enabled,thenARINCbit9

CWSTR

tothereceiverlogicinputs

controlwordbits

mustmatchthisbit

mustmatchthisbit

controlwordbits

mustmatchthisbit

ARINC429DATAFORMAT

Thefollowingtableshowsthebitpositionsinexchangingdatawith
thereceiverorthetransmitter.ARINCbit1isthefirstbit
transmittedorreceived.

BYTE1

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC13121110931303212345678

BIT

BYTE2

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC29282726252423222120191817161514

BIT

THERECEIVERS

ARINCBUSINTERFACE

Figure1showstheinputcircuitforeachreceiver.TheARINC429
specificationrequiresthefollowingdetectionlevels:

STATEDIFFERENTIALVOLTAGE

ONE+6.5Voltsto+13Volts

NULL+2.5Voltsto-2.5Volts

ZERO-6.5Voltsto-13Volts

BD11--enabled,thenARINCbit10

IfReceiver2Decoderis

mustmatchthisbit

INVERTLogic0enablesnormaloddparity

BD12XMTR1=ENABLEandLogic1enablesevenparity

PARITYoutputintransmitter32ndbit

BD13XMTRDATA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainXMTRdataclock

BD14RCVRDTA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainRCVRdataclock

TheHI-8382guaranteesrecognitionoftheselevelswithacommon
modeVoltagewithrespecttoGNDlessthan±5Vfortheworstcase
condition(4.75Vsupplyand13Vsignallevel).

Thetolerancesinthedesignguaranteedetectionoftheabove
levels,sotheactualacceptancerangesareslightlylarger.Ifthe
ARINCsignalisoutoftheactualacceptanceranges,includingthe
nulls,thechiprejectsthedata.

HOLTINTEGRATEDCIRCUITS

3

HI-3282

FUNCTIONALDESCRIPTION(con't)

RECEIVERLOGICOPERATION

Figure2showsablockdiagramofthelogicsectionofeachreceiver.

BITTIMING

TheARINC429specificationcontainsthefollowingtiming
specificationforthereceiveddata:

HIGHSPEEDLOWSPEED

BITRATE

PULSERISETIME

PULSEFALLTIME

PULSEWIDTH

100KBPS±1%12K-14.5KBPS

1.5±0.5µsec10±5µsec

1.5±0.5µsec10±5µsec
5µsec±5%34.5to41.7µsec

RECEIVERPARITY

ThereceiverparitycircuitcountsOnesreceived,includingthe
paritybit,ARINCbit32.Iftheresultisodd,then"0"willappearin
the32ndbit.

TOPINS

RETRIEVINGDATA

Once32validbitsarerecognized,thereceiverlogicgenerates
anEndofSequence(EOS).Ifthereceiverdecoderisenabled
andthe9thand10thARINCbitsmatchthecontrolword
programbitsorifthereceiverdecoderisdisabled,thenEOS
clocksthedatareadyflagflipfloptoa"1",or(orboth)

D/R1D/R2

willgolow.Thedataflagforareceiverwillremainlowuntilafter

ARINCbytesfromthatreceiverareretrieved.Thisis

both
accomplishedbyactivatingwithSEL,thebyteselector,low
toretrievethefirstbyteandactivatingwithSELhighto
retrievethesecondbyte.retrievesdatafromreceiver1and

ret rievesdatafromreceiver2.

EN2

EN

EN

ENI

IfanotherARINCwordisreceived,andanewEOSoccurs
beforethetwobytesareretrieved,thedataisoverwrittenbythe
newword.

DECODER
CONTROL

BITS

SEL

EN

D/R

ZEROS

ONES

NULL

MUX

CONTROL

LATCH

ENABLE

/

CONTROL

BITS9&10

EOS

SHIFTREGISTER

SHIFTREGISTER

SHIFTREGISTER

32TO16DRIVER

32BITLATCH

32BITSHIFTREGISTER

DATA

BITCLOCK

WORDGAP

START

CONTROL

BITBD14

PARITY
CHECK

WORDGAP

SEQUENCE

CONTROL

DETECTION

TIMER

ERROR

32ND

CLOCK

OPTION

CLOCK

BIT

COUNTER

AND

BIT

SEQUENCE

EOS

BITCLOCK

END

ERROR

CLOCK

ENDOF

CLK

FIGURE2. RECEIVERBLOCKDIAGRAM

HOLTINTEGRATEDCIRCUITS

4

TRANSMITTER

AblockdiagramofthetransmittersectionisshowninFigure3.

HI-3282

TRANSMITTERPARITY

ControlregisterbitBD04(PAREN)enablesparitybitinsertioninto
transmitterdatabit32.ParityisalwaysinsertedifDBCENisopen
orhigh.IfDBCENislow,logic0onPARENinsertsdataonbit32,
andlogic1onPARENinsertsparityonbit32.

FIFOOPERATION

TheFIFOisloadedsequentiallybyfirstpulsingtoloadbyte1
andthentoloadbyte2.Thecontrollogicautomaticallyloads
the31bitwordinthenextavailablepositionoftheFIFO.IfTX/R,
thetransmitterreadyflagishigh(FIFOempty),then8words,
each31bitslong,maybeloaded.IfTX/Rislow,thenonlythe
availablepositionsmaybeloaded.Ifall8positionsarefull,the
FIFOignoresfurtherattemptstoloaddata.

PL2

PL1

DATATRANSMISSION

WhenENTXgoeshigh,enablingtransmission,theFIFO
positionsareincrementedwiththetopregisterloading intothe
datatransmissionshiftregister.Within2.5dataclocksthefirst
databitappearsateither429DOor.The31bitsinthe
datatransmissionshiftregisterarepresentedsequentiallytothe
outputsintheARINC429formatwiththefollowingtiming:

ARINCDATABITTIME10Clocks80Clocks

DATABITTIME5Clocks40Clocks
NULLBITTIME5Clocks40Clocks

WORDGAPTIME40Clocks320Clocks

Thewordcounterdetectswhenallloadedpositionsare
transmittedandsetsthetransmitterreadyflag,TX/R,high.

429DO

HIGHSPEEDLOWSPEED

TheparitygeneratorcountstheONESinthe31-bitword.Ifthe
BD12controlwordbitissetlow,the32ndbittransmittedwillmake
parityodd.Ifthecontrolbitishightheparityiseven.

SELFTEST

IftheBD05controlwordbitissetlow,429DOorbecome
inputstothereceiversbypassingtheinterfacecircuitry.
and 429DO

outputsremainactiveduringselftest.

429DO

429DO

SYSTEMOPERATION

Thetworeceiv ersareindependentofthetransmitter.Therefore,
controlofdataexchangesarestrictlyattheoptionoftheuser.The
onlyrestrictionsare:

1.Thereceiveddatamaybeoverwrittenifnotretrieved

withinoneARINCwordcycle.

2.TheFIFOcanstore8wordsmaximumandignores
attemptstoloadadditiondataiffull.

3.Byte1ofthetransmitterdatamustbeloadedfirst.

4.Eitherbyteofthereceiveddatamayberetrievedfirst.

Bothbytesmustberetrievedtoclearthedatareadyflag.

5.AfterENTX,transmissionenable,goeshighitcannotgo
lowuntilTX/R,transmitterreadyflag,goeshigh.O therwise,
oneARINCwordislostduringtransmission.

HOLTINTEGRATEDCIRCUITS

5

HI-3282

REPEATEROPERATION

Therepeatermodeofoperationallowsadatawordthathasbeen
receivedbytheHI-3282tobeplaceddirectlyintoitsFIFOfor
transmission.Aftera32-bitwordhasbeenshiftedintothereceiver
shiftregister,theflagwillgolow.Alogic"0"isplacedontheSEL
lineandisstrobed.Thisisthesameprocedureasfornormal

EN
receiveroperationanditplacesthelowerbyte(16)ofthedataword
onthedatabus.Bystrobingatthesame

429DO

429DO

D/R

DATA

ARINCBIT

BIT30

NULL

DATA

PL1

BIT31

NULL

DATA

timeas,thebytewillalsobeplacedintothetransmitterFIFO.
SEListhentakenhighandisstrobedagaintoplacetheupper
byteofthedatawordonthedatabus.Bystrobingatthesame
timeas,thesecondbytewillalsobeplacedintotheFIFO.The

EN

EN

PL2

EN
datawordisnowreadytobetransmittedaccordingtotheparity
programmedintothecontrolwordregister.

Innormaloperation,eitherbyteofareceiveddatawordmayberead
fromthereceiverlatchesfirstbyuseofSELinput.Duringrepeater
operationhowever,thelowerbyteofthedatawordmustberead
first.Thisisnecessarybecause,asthedataisbe ingread,itisalso
beingloadedintotheFIFOandthetransmitterFIFOisalways
loadedwiththelowerbyteofthedatawordfirst.

NULL

BIT32

WORDGAP

BIT1

NEXTWORD

DATABUS

CWSTR

DATABUS

VALID

t

CWSET

t

CWSTR

t

D/R

t

SELEN

t

D/REN

t

ENDATA

t

ENSEL

t

CWHLD

t

DATAEN

t

ENEN

t

ENDATA

t

SELEN

t

END/R

t

EN

t

ENSEL

t

DATAEN

HOLTINTEGRATEDCIRCUITS

6

HI-3282

DATABUS

PL1

PL2

TX/R

PL2

TX/R

ENTX

429DO

or

429DO

t

PL2EN

t

ENDAT

t

PL

ARINCBIT

DATA
BIT1

BYTE1VALID

t

DWSET

t

DWHLD

t

PL12

DATA
BIT2

t

PL

BYTE2VALID

t

DWSET

t

DWHLD

t

TX/R

t

PL12

t

DTX/R

DATA

BIT32

t

ENTX/R

429DI

SEL

TX/R

ENTX

429DO

D/R

EN

PL1

PL2

BIT32

t

D/R

t

DON'TCARE

SELEN

t

D/REN

t

ENPL

t

END/R

t

EN

t

PLEN

t

ENEN

t

ENSEL

t

ENPL

t

t

SELEN

t

TX/REN

EN

DON'TCARE

t

ENSEL

t

PLEN

t

TX/R

t

ENTX/R

t

ENDAT

BIT1 BIT32

t

DTX/R

t

NULL

HOLTINTEGRATEDCIRCUITS

7

HI-3282

SupplyVoltageVcc

-0.5Vto+7V
Voltageatpins2,3,4&5-29Vto+29V
Voltageatanyotherpin-1.5VtoVcc+1.5V
DCCurrentDrainperinputpin10mA

PowerDissipation500mW
OperatingTemperatureRange:(Industrial)-40°Cto+85°C

(Military)-55°Cto+125°C

StorageTemperatureRange:-65°Cto+150°C

NOTE:Stressesabovethoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.Thesea restressratingsonly.
Functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsection softhespecificationsisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.

Vcc=5V±5%,GND=0V,TA=OperatingTemperatureRange(unlessotherwisespecified).

LIMITS

PARAMETERCONDITIONSUNITSYMBOL

ARINCINPUTS-Pins:429DI1(A),429DI1(B),429DI2(A),429DI2(B)

DifferentialInputVoltage:ONEVCommon6.510.013.0V

ZEROVmodevoltagelessthan±5V-13.0-10.0-6.5V

NULLVwithrespecttoGND-2.502.5V

InputResistance:DifferentialR12K

ToGNDR1227K

ToVccR1227k

InputCurrent:InputSinkI200µA

InputSourceI-450µA

IH
IL

NUL

I
G
H

IH
IL

MINTYPMAX

Ω
Ω
Ω

InputCapacitance:DifferentialC20pF

(Guaranteedbutnottested)ToGNDC20pF

ToVccC20pF

I
G
H

BI-DIRECTIONALINPUTS-Pins:BD00-BD15

InputVoltage:InputVoltageHIV2.0V

InputVoltageLOV0.8V

InputCurrent:InputSinkI1.5µA

InputSourceI-1.5µA

IH
IL

IH
IL

ALLOTHERINPUTS

InputVoltage:InputVoltageHIV2.0V

InputVoltageLOV0.8V

InputCurrent:InputSinkI10µA

InputSourceI-10µA

Pull-upCurr ent(Pin)I-150-50A

DCBEN µ

IH
IL

IH
IL

PU

OUTPUTS

OutputVoltage:Logic"1"OutputVoltageVI=-1.5mA2.7V

Logic"0"OutputVoltageVI=1.6mA0.4V

OutputCurrent:OutputSinkIV=0.4V1.6mA

(Bi-directionalPins)OutputSourceIV=V-0.4V-1.0mA

OutputCurrent:OutputSinkIV=0.4V1.6mA

(AllOtherOutputs)OutputSourceIV=V-0.4V-1.0mA

OutputCapacitance:C15pF

OHOH
OLOL

OLOUT
OHOUTCC

OLOUT
OHOUTCC

O

SUPPLYINPUT

StandbySupplyCurrent:I10mA
OperatingSupplyCurrent:I10mA

CC1

CC2

HOLTINTEGRATEDCIRCUITS

8

HI-3282

Vcc=5V,GND=0V,TA=OperatingTemperatureRangeandfclk=1mhz0.1%with60/40dutycycle+

PARAMETERSYMBOLUNITS

CONTROLWORDTIMING

RECEIVERTIMING

Delay-StartARINC32ndBittoLOW:HighSpeedt16µs

FIFOTIMING

TRANSMISSIONTIMING

Delay-ENTXHIGHto429DOor:HighSpeedt25µs
Delay-ENTXHIGHto4 29DOor:LowSpeedt200µs

REPEATEROPERATIONTIMING

MasterResetPulseWidth
ARINCDataRateandBitTiming

LIMITS

MINTYPMAX

Setup-DATABUSValidtoHIGHt50ns

PulseWidth-t50ns

Hold-HIGHtoDATABUSHi-Zt0ns

CWSTR

D/R

Delay-LOWtoL0Wt0ns

Delay-LOWtoHIGHt200ns

D/REN

END/R

Setup-SELtoL0Wt0ns

Hold-SELtoHIGHt0ns

Delay-L0WtoDATABUSValidt5080ns

EN

Delay-HIGHtoDATABUSHi-Zt30ns

EN

PulseWidth-ort8050ns

Spacing-HIGHtonextL0Wt50ns

ENEN

PulseWidth-ort50ns

Setup-DATABUSValidtoHIGHt50ns

Hold-HIGHtoDATABUSHi-Zt0ns

PL

Spacing-ort0ns

Delay-HIGHtoTX/RLOWt840ns

PL2

Spacing-HIGHtoENTXHIGHt0µs

PL2

429D0
429D0

Delay-32ndARINCBittoTX/RHIGHt50ns

Spacing-TX/RHIGHtoENTXL0Wt0ns

Delay-LOWtoLOWt0ns

ENPL

Hold-HIGHtoHIGHt0ns

PLEN

Delay-TX/RLOWtoENTXHIGHt0ns

CWSTR

CWSTR

LowSpeedt128µs

EN

EN

EN1EN2

PL1PL2

PL

PL1PL2

CWSTR
CWSET
CWHLD

D/R
D/R

D/REN
END/R

SELEN
ENSEL

ENDATA
DATAEN

EN

ENEN

PL

DWSET
DWHLD

PL12

TX/R

PL2EN

ENDAT
ENDAT

DTX/R

ENTX/R

ENPL

PLEN

TX/REN

t50ns

MR

±1%

HOLTINTEGRATEDCIRCUITS

9

HI-3282

ADDITIONALHI-3282PINCONFIGURATIONS (Seepage1forthe44-pinPlasticQFP)

PINCONFIGURATION (TopView)

HOLTINTEGRATEDCIRCUITS

10

HI-3282

PART
NUMBER

HI-3282PQT

HI-3282PJI

HI-3282CDT
HI-3282CDM

PACKAGE
DESCRIPTION

44PINPLASTICQUADFLATPACK(PQFP)
44PINPLASTICQUADFLATPACK(PQFP)

44PINPLASTICJ-LEADPLCC

44PINPLASTICJ-LEADPLCC
40PINCERAMICSIDE-BRAZEDDIP
40PINCERAMICSIDE-BRAZEDDIP

40PINCERAMICSIDE-BRAZEDDIP

TEMPERATURE
RANGE

-40°CTO+85°CHI-3282PQI NO SOLDER

-55°CTO+125°C

-40°CTO+85°C I

-40°CTO+85°CHI-3282CDI NO GOLD

-55°CTO+125°C

-55°CTO+125°C

FLOW BURN

IN

I

T

T
I

T

M

NO SOLDER
NO SOLDER

NO GOLD

YES SOLDER

LEAD

FINISH

SOLDERNO-55°CTO+125°CHI-3282PJT

HOLTINTEGRATEDCIRCUITS

11

40-PINCERAMICSIDE-BRAZEDDIP

(51.308MAX)

HI-3282PACKAGEDIMENSIONS

inches(millimeters)

PackageType:

2.020MAX

40C

.610 ± .010

(15.494 ± .254)

.225MAX

(5.715MAX)

.125MIN

(3.175MIN)

44-PINPLASTICPLCC

PINNO.1

.045x45°

.690 ± .005

(17.526 ± .127)

SQ.

.018TYP

(.457TYP)

PINNO.1IDENT

.050TYP

(1.270TYP)

.653 ± .004

(16.586 ± .102)

SQ.

(2.159 ± .229)

.100BSC

(2.540BSC)

.045x45°

.085 ± .009

.595 ± .010

(15.113 ± .254)

.010 + .002 /− .001

(.254 + .051 /− .025)

.050 ± .005

(1.27 ± .127)

.600 ± .010

(15.240 ± .254)

PackageType:

.031 ± .005

(.787 ± .127)

44J

.172 ± .008

(4.369 ± .203)

SEEDETAIL

A

.610 ± .020

(15.494 ± .508)

HOLTINTEGRATEDCIRCUITS

12

.009
.011

DETAILA

.017 ± .004

(.432 ± .102)

.015±.002

(.381 ± .051)

.020MIN

(.508 ΜΙΝ )
.025

R

.045

HI-3282PACKAGEDIMENSIONS

44-PINPLASTICQUADFLATPACK(PQFP)

.097

(2.45)

.547±.010

(13.90±.25)

SQ.

SeeDetailA

MAX.

.394±.004
(10.0±.10)

SQ.

.079+.004/-.006

(2.00+.10/-.15)

.008

(.20R)

TYP.

PackageType:

.007

MAX.

(.17)

.0315BSC

(.80BSC)

.014±..002

(.35±.05)

.035+.006/-.004

(.88+.15/-.10)

.012

TYP.

(.30R)

DetailA

inches(millimeters)

44PQS

0 °≤Θ≤ 7 °

HOLTINTEGRATEDCIRCUITS

13