Page 1
TM
HI-1818A, HI-1828A
Data Sheet July 1999
Low Resistance, Single 8-Channel, and
Differential 4-Channel, CMOS Analog
Multiplexers
The Hl-1818A and HI-1828A are monolithic, high
performance CMOS analog multiplexers offering built-in
channel selection decoding plus an inhibit (enable) input for
disabling all channels. Dielectric Isolation (Dl) processing is
used for enhanced reliability and performance (see
Application Note 521). Substrate leakage and parasitic
capacitance are much lower, resulting in extremelylowstatic
errors and high throughput rates. Low output leakage
(typically 0.1nA) and low channel ON resistance (250Ω)
assure optimum performance in low level or current mode
applications.
The HI-1818A is a single-ended, 8-Channel multiplexer, while
the HI-1828A is a differential 4-Channel version. Either de vice
is ideally suitedformedical instrumentation,telemetry systems,
and microprocessor based data acquisition systems.
For MIL-STD-883 compliant parts, request the HI-1818A/883.
File Number 3141.2
Features
• Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
• “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Ω
• Input Leakage (Max) . . . . . . . . . . . . . . . . . . . . . . . . 50nA
• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350ns
• Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 5mW
• DTL/TTL Compatible Address
o
• Operation . . . . . . . . . . . . . . . . . . . . . . . . . -55
C to 125oC
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
Ordering Information
Pinouts
ADDRESS A
ADDRESS A
+5V SUPPLY
ENABLE
IN 8
IN 7
IN 6
IN 5
HI-1818A (CERDIP)
TOP VIEW
1
1
2
3
4
2
5
6
7
8
16
ADDRESS A
15
-V
SUPPLY
14
+V
SUPPLY
13
IN 1
12
OUT
11
IN 2
10
IN 3
9
IN 4
PART NUMBER
TEMP.
RANGE (oC) PACKAGE
PKG.
NO.
HI1-1818A-2 -55 to 125 16 Ld CERDIP F16.3
HI1-1818A-5 0 to 75 16 Ld CERDIP F16.3
HI1-1828A-2 -55 to 125 16 Ld CERDIP F16.3
HI3-1828A-5 0 to 75 16 Ld PDIP E16.3
HI-1828A (CERDIP, PDIP)
TOP VIEW
16
ADDRESS A
15
-V
SUPPLY
14
+V
SUPPLY
13
IN 1
12
OUT 1 THRU 4
11
IN 2
10
IN 3
9
IN 4
0
IN 8
IN 7
IN 6
IN 5
1
1
2
3
4
5
6
7
8
0
ADDRESS A
+5V SUPPLY
ENABLE
OUT 5 THRU 8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Copyright © Intersil Corporation 1999
Page 2
Truth Tables
HI-1818A TRUTH TABLE
ADDRESS
2
A
1
A
EN
0
“ON” CHANNELA
LLLL 1
LLHL 2
LHLL 3
LHHL 4
HLLL 5
HLHL 6
HHLL 7
HHHL 8
X X X H None
Functional Block Diagrams
DIGITAL ADDRESS
A
0
A
1
HI-1818A, HI-1828A
1
L L L 1 and 5
L H L 2 and 6
H L L 3 and 7
H H L 4 and 8
X X H None
HI-1818A
A
2
ENABLE
HI-1828A TRUTH TABLE
ADDRESS
A
0
EN
“ON” CHANNELA
ADDRESS
INPUT
BUFFERS
ADDRESS
INPUT
BUFFERS
ENABLE
BUFFER
DECODERS
MULTIPLEX
SWITCHES
N
P
N P
IN 1
OUT
IN 8
HI-1828A
A
0
A
1
ENABLE
DECODERS
ENABLE
BUFFER
MULTIPLEX
SWITCHES
N
P
N P
IN 1
OUT 1-4
IN 4
IN 5
N P
OUT 5-8
IN 8
N P
2
Page 3
Schematic Diagrams
HI-1818A, HI-1828A
ADDRESS INPUT BUFFER
P3
All N-Channel Bodies to VAll P-Channel Bodies to V+
Unless Otherwise Specified
All N-Channel Bodies to VAll P-Channel Bodies to V+
A2 or A2 not used for HI-1828A
200Ω
ADDRESS
INPUT
EN
D1
D2
V+
V-
A2 OR
A2
P1
N1
P2
N2
A1 OR
A1
N12N11
V
CC
P4
N4
N3
ADDRESS DECODER
V+
P11
P12
A0
P13
P14
N14
A0 OR
N13
P5
A
P7
P6
N7
N6
N5
V-
P15
N15
P8
N8
P16
N16
P9
N9
TO P-CHANNEL
SWITCH
TO N-CHANNEL
SWITCH
P10
N10
A
All N-Channel Bodies to VAll P-Channel Bodies to V+
Unless Otherwise Specified
V-
IN SWITCH CELL
MULTIPLEXER SWITCH
FROM DECODE
N18
V+
N19
P17
FROM DECODE
N17
OUTIN
V+
P18
3
Page 4
HI-1818A, HI-1828A
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Logic Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Analog Signal (VIN, V
). . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
OUT
Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . (V-) to (V+)
Operating Conditions
Temperature Ranges
HI-1818A/HI-1828A-2. . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-1818A/HI-1828A-5. . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . . 85 32
PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Electrical Specifications Supplies = +15V, -15V, +5V; V
TEST
PARAMETER
CONDITIONS
= 0.4V, VAH = 4.0V, Unless Otherwise Specified
AL
TEMP
o
(
C)
-2 -5
UNITSMIN TYP MAX MIN TYP MAX
DYNAMIC CHARACTERISTICS
Access Time, t
A
Note 4 25 - 350 500 - 350 - ns
Full - - 1000 - - 1000 ns
Break-Before-Make Delay, t
Enable Delay (ON), t
ON(EN)
OPEN
25 - 25 - - 100 - ns
25 - 300 500 - 300 - ns
Full - - 1000 - - 1000 ns
Enable Delay (OFF), t
OFF(EN)
25 - 300 500 - 300 - ns
Full - - 1000 - - 1000 ns
Settling Time To 0.1% 25 - 1.08 - - 1.08 - µs
To 0.025% 25 - 2.8 - - 2.8 - µs
Channel Input Capacitance, C
Channel Output Capacitance, C
S(OFF)
D(OFF)
25 - 4 - - 4 - pF
-
HI-1818A 25 - 20 - - 20 - pF
HI-1828A 25 - 10 - - 10 - pF
Input to Output Capacitance, C
Digital Input Capacitance, C
A
DS(OFF)
25 - 0.6 - - 0.6 - pF
25 - 5 - - 5 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
Input High Threshold, V
Input Leakage Current, I
AL
AH
Note 3 Full 4.0 - - 4.0 - - V
A
Full - - 0.4 - - 0.4 V
Full - - 1 - - 1 µA
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, V
ON Resistance, r
ON
lN
Note 2 25 - 250 400 - 250 400 Ω
Full -15 - +15 -15 - +15 V
Full - - 500 - - 500 Ω
OFF Input Leakage Current, I
ON Channel Leakage Current, l
S(OFF)
D(ON)
Full - - 50 - - 50 nA
Hl-1818A Full - - 250 - - 250 nA
HI-1828A Full - - 125 - - 125 nA
OFF Output Leakage Current, I
D(OFF)
HI-1818A Full - - 250 - - 250 nA
HI-1828A Full - - 125 - - 125 nA
4
Page 5
HI-1818A, HI-1828A
Electrical Specifications Supplies = +15V, -15V, +5V; V
TEST
PARAMETER
CONDITIONS
= 0.4V, VAH = 4.0V, Unless Otherwise Specified (Continued)
AL
TEMP
-2 -5
(oC)
UNITSMIN TYP MAX MIN TYP MAX
POWER SUPPLY CHARACTERISTICS
Power Dissipation, P
D
Full - - 27.5 - - 27.5 mW
Current, I+ Full - - 0.5 - - 0.5 mA
Current, I- Full - - 1 - - 1 mA
Current, I
L
Full - - 1 - - 1 mA
NOTES:
2. V
OUT
= ±10V, I
OUT
±
= 1mA.
3. To drive from DTL/TTL circuits, 1kΩ pull-up resistors to 5.0V supply are recommended.
4. Time measured to 90% of final output level; V
= -5.0V to 5.0V, Digital Inputs = 0V to 4.0V.
OUT
Test Circuits and Waveforms
+15V
-15V +5V
ENABLE DRIVE
2V/DIV.
DISABLED
ENABLED
100ns/DIV.
ON)
(S
1
OUTPUT
2V/DIV.
VAH = 4.0V
50%
V
t
ON
(EN)
AL
= 0V
90%
ENABLE DRIVE
(VA)
OUTPUT
10%
t
OFF
(EN)
FIGURE 1A. MEASUREMENT POINTS
V+ V- V
A
2
HI-1818A
A
1
(NOTE 5)
A
0
EN
50
V
A
Ω
L
IN 1
IN 2-8
OUT
NOTE:
5. Similar connections for HI-1828A.
FIGURE 1B. TEST CIRCUIT FIGURE 1C. WAVEFORMS
FIGURE 1. ENABLE DELAYS
200
+5V
12.5
pF
Ω
4.0V
ADDRESS
DRIVE (V
0V
50%50%
t
OPEN
A
OUTPUT
FIGURE 2A. MEASUREMENT POINTS
5
+15V
-15V +5V
V+ V- V
A
2
A
1
HI-1818A
(NOTE 6)
EN
)
V
A
A
0
50
Ω
IN 3-8
OUT
NOTE:
6. Similar connections for HI-1828A.
FIGURE 2B. TEST CIRCUIT FIGURE 2C. WAVEFORMS
FIGURE 2. BREAK-BEFORE-MAKE DELAY
IN 1
IN 2
L
200
+5V
12.5
Ω
pF
VA INPUT
2V/DIV.
S2 ONS1 ON
OUTPUT
1V/DIV.
100ns/DIV.
Page 6
1mA
V
HI-1818A, HI-1828A
2
IN
V
IN
350
300
250
200
ON RESISTANCE (Ω)
150
100
-10-8-6-4-20246810
OUT
ANALOG INPUT (V)
RON =
V
2
1mA
125oC
25oC
-55oC
V
60
40
20
0
-20
125oC
SWITCH CURRENT (mA)
-40
-55oC
-60
-10-8-6-4-20246810
25oC
VOLTAGE ACROSS SWITCH (V)
OUT
A
-55oC
25oC
FIGURE 3. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 4. ON CHANNEL CURRENT vs VOLTAGE
OFF LEAKAGE ON LEAKAGE
4V
EN
OUT
I
D(OFF)
±10V
+10V
A
+10V
EN
A
A
1
0
OUT
0.4V
I
A
D(ON)
±10V
ACCESS TIME TEST CIRCUIT
IN 1
+5V
IN 2
-5V
IN 3-8
HI-1818A†
A1A
0
2
OUT
10
50pF
kΩ
ENA
125oC
S(OFF)
±10V
100nA
100pA
NOTE:
OUT
Two measurements per channel:
±10V and 10V
4V
Twomeasurementsperdevicefor
I
D(OFF)
I
S(OFF)
HI-1818A
HI-1828A
+10V
- I
EN
D(OFF)
TEMPERATURE (
A
10nA
I
D(ON)
HI-1818A
HI-1828A
1nA
10pA
25 50 75 100 125
±
: ±10V and 10V
o
C)
0V TO 4V
±
† Similar connection for HI-1828A.
50%
+5V
50Ω
4V
10%
t
A
100ns/DIV.
FIGURE 5. LEAKAGE CURRENTS vs TEMPERATURE FIGURE 6. ACCESS TIME
6
A0INPUT
2V/DIV.
OUTPUT
5V/DIV.
-5V
Page 7
Die Characteristics
HI-1818A, HI-1828A
DIE DIMENSIONS:
67.7 mils x 103.5 mils
METALLIZATION:
Type: CuAl
Thickness: 16k
Å ±2kÅ
Metallization Mask Layout
HI-1818A HI-1828A
EN
A
IN 8
V
L
2
A
1
A
0
-V
SUPPLY
+V
SUPPLY
IN 1
OUTPUT
PASSIVATION:
Type: Nitride/Silox
Thickness: Silox: 12k
Å ±2kÅ, Nitride: 3.5kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
5
1.43 x 10
EN
OUT 5
THRU 8
IN 8
A/cm2 at 25mA
V
L
A
1
A
0
-15V
SUPPLY
+V
SUPPLY
IN 1
OUT 1
THRU 4
IN 7
IN 2IN 3IN 4IN 5IN 6
IN 7
IN 2IN 3IN 4IN 5IN 6
7
Page 8
Dual-In-Line Plastic Packages (PDIP)
HI-1818A, HI-1828A
N
D1
-C-
E1
-B-
A1
A2
E
A
L
e
C
C
L
e
A
C
e
B
INDEX
AREA
BASE
PLANE
SEATING
PLANE
D1
B1
1 2 3 N/2
-AD
e
B
0.010 (0.25) C AM BS
NOTES:
1. ControllingDimensions:INCH.Incase of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. Eand are measured with the leads constrained tobe perpendic-
e
A
ular to datum .
-C-
7. eBand eCare measured at the lead tipswith the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC e
A
e
B
0.300 BSC 7.62 BSC 6
- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
NOTESMIN MAX MIN MAX
Rev. 0 12/93
8
Page 9
HI-1818A, HI-1828A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
LEAD FINISH
c1
-A-
-B-
bbb C A - B
S
BASE
PLANE
SEATING
PLANE
S1
b2
ccc C A - BMD
D
A
A
b
e
S
S
NOTES:
1. Indexarea: A notch ora pin oneidentification mark shall belocated adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
-DBASE
E
D
S
S
Q
A
-CL
METAL
b1
M
(b)
SECTION A-A
α
(c)
M
eA
eA/2
aaa C A - B
M
c
D
S S
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
o
α
90
105
o
90
o
105
aaa - 0.015 - 0.38 bbb - 0.030 - 0.76 ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N16 168
NOTESMIN MAX MIN MAX
o
Rev. 0 4/94
-
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
9
EUROPE
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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Taipei, Taiwan 104
Republic of China
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