• Typical Fall Time . . . . . . . . . . . . . . 130ns at T
= 150oC
J
• Short Circuit Rating
• Low Conduction Loss
• Hyperfast Anti-Parallel Diode
Description
The HGTP3N60C3D, HGT1S3N60C3D, and HGT1S3N60C3DS
are MOS gated high voltage switching devices combining the
best features of MOSFETs and bipolar transistors. These
devices have the high input impedance of a MOSFET and the
low on-state conduction loss of a bipolar transistor. The much
lower on-state voltage drop varies only moderately between
o
25
C and 150oC. The IGBT used is the development type
TA49113. The diode used in anti-parallel with the IGBT is the
development type TA49055.
The IGBT is ideal for many high voltage switching applications
operating at moderate frequencies where low conduction losses
are essential.
) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and
OFF
ending at the point where the collector current equals zero (ICE = 0A). The HGTP3N60C3D, HGT1S3N60C3D, and HGT1S3N60C3DS
were tested per JEDEC standard No. 24-1 Method for Measurement of P ower De vice Turn-Off Switching Loss. This test method produces
the true total Turn-Off Energy Loss. Turn-On losses include diode losses.
HARRIS SEMICONDUCTOR IGBT PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS:
FIGURE 15. CAPACITANCE AS A FUNCTION OF COLLECTOR-
EMITTER VOLTAGE
0
10
0.5
0.2
0.1
-1
10
0.05
0.02
-2
10
10
0.01
SINGLE PULSE
-5
-4
10
-3
10
t1, RECTANGULAR PULSE DURATION (s)
, NORMALIZED THERMAL RESPONSE
JC
θ
Z
, COLLECTOR - EMITTER VOLTAGE (V)
CE
V
-2
10
360
240
120
0
2468101214
0
QG, GATE CHARGE (nC)
FIGURE 16. GATE CHARGE WAVEFORMS
DUTY FACTOR, D = t1 / t
PEAK TJ = (PDX Z
-1
10
= 600V
V
CE
VCE = 400V
VCE = 200V
IG REF = 1.060mA
RL = 200Ω
T
= 25oC
C
t
1
P
D
t
2
2
X R
JC
θ
0
10
) + T
JC
θ
9
6
, GATE-EMITTER VOLTAGE (V)
3
GE
V
0
C
1
10
FIGURE 17. IGBT NORMALIZED TRANSIENT THERMAL IMPEDANCE, JUNCTION TO CASE
3-13
Page 6
HGTP3N60C3D, HGT1S3N60C3D, HGT1S3N60C3DS
Typical Performance Curves
15
12
9
100oC
6
, FORWARD CURRENT (A)
EC
3
I
0
02.0
0.51.01.52.53.0
FIGURE 18. DIODE FORWARD CURRENT AS A FUNCTION OF
FORWARD VOLTAGE DROP
150oC
VEC, FORWARD VOLTAGE (V)
(Continued)
25oC
3.5
Test Circuit and Waveform
30
TC = 25oC, dIEC/dt = 200A/µs
25
20
15
10
, RECOVERY TIMES (ns)
R
t
5
0
0.5
FIGURE 19. RECOVERY TIMES AS A FUNCTION OF FORWARD
CURRENT
14
IEC, FORWARD CURRENT (A)
t
rr
t
A
t
B
L = 1mH
RHRD460
RG = 82Ω
+
V
= 480V
DD
-
FIGURE 20. INDUCTIVE SWITCHING TEST CIRCUITFIGURE 21. SWITCHING TEST WAVEFORMS
V
GE
V
CE
90%
I
CE
t
D(OFF)I
10%
t
90%
E
FI
OFF
E
ON
Operating Frequency Information
Operating frequency information for a typical de vice (Figure 13)
is presented as a guide for estimating device performance
for a specific application. Other typical frequency vs collector
current (I
) plots are possible using the information shown
CE
for a typical unit in Figures 4, 7, 8, 11 and 12. The operating
frequency plot (Figure 13) of a typical device shows f
f
whichever is smaller at each point. The information is
MAX2
MAX1
based on measurements of a typical device and is bounded
by the maximum rated junction temperature.
f
is defined by f
MAX1
MAX1
= 0.05/(t
D(OFF)I
+ t
D(ON)I
). Deadtime (the denominator) has been arbitrarily held to 10% of
the on- state time for a 50% duty factor. Other definitions are
possible. t
D(OFF)I
and t
are defined in Figure 21.
D(ON)I
Device turn-off delay can establish an additional frequency
limiting condition for an application other than T
t
D(OFF)I
is important when controlling output ripple under a
JMAX
lightly loaded condition.
f
is defined by f
MAX2
allowable dissipation (P
T
)/R
C
. The sum of device switching and conduction
θJC
losses must not exceed P
= (PD - PC)/(E
MAX2
) is defined by PD = (T
D
. A 50% duty factor was used
D
(Figure 13) and the conduction losses (P
mated by P
or
and E
E
ON
shown in Figure 21. E
power loss (I
=(VCE x ICE)/2.
C
are defined in the switching waveforms
OFF
x VCE) during turn-on and E
CE
is the integral of the instantaneous
ON
gral of the instantaneous power loss during turn-off. All tail
losses are included in the calculation for E
lector current equals zero (I
CE
= 0).
.
10%
t
RI
t
D(ON)I
+ EON). The
OFF
) are approxi-
C
OFF
OFF
JMAX
is the inte-
; i.e. the col-
-
3-14
Page 7
HGTP3N60C3D, HGT1S3N60C3D, HGT1S3N60C3DS
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to gateinsulation damage by the electrostatic discharge of energy
through the devices. When handling these devices, care
should be exercised to assure that the static charge built in
the handler’s body capacitance is not discharged through
the device. With proper handling and application procedures,
however, IGBTs are currently being extensively used in production by numerous equipment manufacturers in military,
industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. IGBTs can be
handled safely if the following basic precautions are taken:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs or by the insertion into conductive material such
as ECCOSORBD LD26 or equivalent.
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
ECCOSORBD
is a Trademark of Emerson and Cumming, Inc.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
5. Gate Voltage Rating- Never exceed the gate-voltage rat-
ing of V
. Exceeding the rated VGE can result in
GEM
permanent damage to the oxide layer in the gate region.
6. Gate Termination - The gates of these de vices are essen-
tially capacitors. Circuits that leave the gate open-circuited
or floating should be avoided. These conditions can result
in turn-on of the device due to voltage buildup on the input
capacitor due to leakage currents or pickup.
7. Gate Protection - These devices do not have an internal
monolithic zener diode from gate to emitter. If gate protection is required an external zener is recommended.
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems cer tification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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