45A, 1200V, UFS Series N-Channel IGBT
with Anti-Parallel Hyperfast Diode
The HGTG20N120C3D is a MOS gated high voltage
switching device combining the best features of MOSFETs
and bipolar transistors. This device has the high input
impedance of a MOSFET and the low on-state conduction
loss of a bipolar transistor. The much lower on-state voltage
drop varies only moderately between 25
The IGBT is ideal for many high voltage switching
applications operating at moderate frequencies where low
conduction losses are essential, such as: AC and DC motor
controls, power supplies and drivers for solenoids, relays
and contactors.
The diode used in anti-parallel with the IGBT was formerly
developmental type TA49155.
The IGBT diode combination was formerly developmental
type TA49264.
o
C and 150oC.
Features
• 45A, 1200V, TC = 25oC
• 1200V Switching SOA Capability
• Typical Fall Time. . . . . . . . . . . . . . . . 300ns at T
Operating and Storage Junction Temperature Range. . . . . . . . . . . . . . . . . . . . .TJ, T
Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Short Circuit Withstand Time (Note 2) at VGE = 15V. . . . . . . . . . . . . . . . . . . . . . . . . . t
Short Circuit Withstand Time (Note 2) at VGE = 12V. . . . . . . . . . . . . . . . . . . . . . . . . . t
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
ARV
STG
L
SC
SC
100mJ
-40 to 150
260
8µs
15µs
o
C
o
C
NOTES:
1. Pulse width limited by maximum junction temperature.
2. V
Electrical SpecificationsT
= 720V, TJ = 125oC, RGE = 3Ω.
CE(PK)
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Collector to Emitter Breakdown VoltageBV
Collector to Emitter Leakage CurrentI
Collector to Emitter Saturation VoltageV
CE(SAT)IC
CES
CES
IC = 250µA, VGE = 0V1200--V
VCE = BV
= I
C110
VGE = 15V
Gate to Emitter Threshold VoltageV
Gate to Emitter Leakage CurrentI
GE(TH)
GES
IC = 250µA, VCE = V
VGE = ±20V--±250nA
Switching SOASSOATJ = 150oC,
RG = 3Ω,
VGE = 15V
L = 100µH,
Gate to Emitter Plateau VoltageV
On-State Gate ChargeQ
GEP
G(ON)
IC = I
IC = I
C110
C110
VCE = 0.5 BV
Current Turn-On Delay Timet
d(ON)I
Current Rise Timet
Current Turn-Off Delay Timet
d(OFF)I
Current Fall Timet
Turn-On Energy (Note 4)E
Turn-On Energy (Note 4)E
Turn-Off Energy (Note 3)E
rI
fI
ON1
ON2
OFF
IGBT and Diode at TJ = 25oC
ICE = I
C110
VCE = 0.8 BV
VGE = 15V
RG= 3Ω
L = 1mH
Test Circuit - (Figure 19)
CES
TC = 25oC--150µA
TC = 150oC--2.0mA
,
TC = 25oC-2.43.0V
TC = 150oC-2.22.9V
GE
V
V
, VCE = 0.5 BV
,
VGE = 15V-93130nC
CES
VGE = 20V-186230nC
CES
5.07.07.5V
= 960V60--A
CE (PK)
= 1200V20--A
CE (PK)
CES
-9.4-V
-39- ns
-22- ns
-110-ns
-95- ns
-950-µJ
-2250-µJ
-12002400µJ
2
Page 3
HGTG20N120C3D
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified (Continued)
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Current Turn-On Delay Timet
d(ON)I
Current Rise Timet
Current Turn-Off Delay Timet
d(OFF)I
Current Fall Timet
Turn-On Energy (Note 4)E
Turn-On Energy (Note 4)E
Turn-Off Energy (Note 3)E
Diode Forward VoltageV
Diode Reverse Recovery Timet
) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending
OFF
at the point where the collector current equals zero (ICE= 0A). All devices were tested per JEDEC Standard No. 24-1 Method for Measurement
of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss.
4. Values for two Turn-On loss conditions are shown for the convenience of the circuit designer. E
is the turn-on loss of the IGBT only. E
ON1
the turn-on loss when a typical diode is used in the test circuit and the diode is at the same TJ as the IGBT. The diode type is specified in
Figure 19.
o
o
C/W
C/W
ON2
is
Typical Performance Curves
45
40
35
30
25
20
15
10
, DC COLLECTOR CURRENT (A)
5
CE
I
0
2575100125150
50
TC, CASE TEMPERATURE (oC)
(Unless Otherwise Specified)
FIGURE 1. DC COLLECTOR CURRENT vs CASE
TEMPERATURE
VGE= 15V
70
TJ= 150oC, RG = 3Ω, VGE= 15V, L = 100µH
60
50
40
30
20
10
, COLLECTOR TO EMITTER CURRENT (A)
0
CE
I
0
V
, COLLECTOR TO EMITTER VOLTAGE (V)
CE
60080040020010001200
1400
FIGURE 2. MINIMUM SWITCHING SAFE OPERATING AREA
3
Page 4
HGTG20N120C3D
Typical Performance Curves
60
10
f
= 0.05 / (t
MAX1
f
= (PD- PC) / (E
MAX2
= CONDUCTION DISSIPATION
P
C
, OPERATING FREQUENCY (kHz)
MAX
f
1
(DUTY FACTOR = 50%)
R
= 0.6oC/W, SEE NOTES
ØJC
5
TJ= 150oC, RG = 3Ω, L = 1mH,
+ t
d(OFF)I
ON2
10
I
, COLLECTOR TO EMITTER CURRENT (A)
CE
d(ON)I
+ E
)
OFF
(Unless Otherwise Specified) (Continued)
V
CE
T
C
o
75
o
75
o
110
110oC
)
FIGURE 3. OPERATINGFREQUENCY vs COLLECTORTO
EMITTER CURRENT
70
DUTY CYCLE <0.5%, V
PULSE DURATION = 250µs
60
50
40
30
20
10
, COLLECTOR TO EMITTER CURRENT (A)
CE
0
I
024
, COLLECTOR TO EMITTER VOLTAGE (V)
V
CE
GE
= 12V
TC = 150oC
TC = 25oC
TC = -40oC
6810
= 960V
C
C
C
V
15V
12V
15V
12V
GE
35400
VCE = 720V, RGE = 3Ω, TJ= 125oC
30
25
20
15
10
, SHORT CIRCUIT WITHSTAND TIME (µs)
6020
5
SC
t
111213141516
VGE, GATE TO EMITTER VOLTAGE (V)
I
SC
350
300
250
200
150
t
SC
, PEAK SHORT CIRCUIT CURRENT (A)
SC
I
100
FIGURE 4. SHORT CIRCUIT WITHSTAND TIME
200
DUTY CYCLE <0.5%, VGE = 15V
175
PULSE DURATION = 250µs
150
125
100
75
50
25
, COLLECTOR TO EMITTER CURRENT (A)
CE
0
I
024
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
6810
TC = -40oC
TC = 150oC
TC = 25oC
1214
FIGURE 5. COLLECTOR TO EMITTER ON-STATE VOLTAGEFIGURE 6. COLLECTOR TO EMITTER ON-STATE VOLTAGE
FIGURE 13. TRANSFER CHARACTERISTICFIGURE 14. GATE CHARGE WAVEFORMS
5
FIGURE 12. FALLTIME vs COLLECTOR TO EMITTER
CURRENT
15
I
= 1mA, RL = 30Ω, TC = 25oC
G (REF)
12
VCE = 1200V
9
VCE = 800V
150100
6
, GATE TO EMITTER VOLTAGE (V)
3
GE
V
0
VCE = 400V
0
50
2575175125
QG, GATE CHARGE (nC)
Page 6
HGTG20N120C3D
Typical Performance Curves
C, CAPACITANCE (pF)
FIGURE 15. CAPACITANCE vs COLLECTOR TO EMITTER VOLTAGE
0
10
0.50
0.20
(Unless Otherwise Specified) (Continued)
8000
7000
6000
5000
4000
3000
2000
1000
0
0510152025
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
C
C
C
IES
OES
RES
FREQUENCY = 1MHz
0.10
-1
10
0.05
0.02
0.01
, NORMALIZED THERMAL RESPONSE
-2
10
θJC
Z
-5
10
SINGLE PULSE
-4
10
-3
10
t1, RECTANGULAR PULSE DURATION (s)
FIGURE 16. NORMALIZED TRANSIENT THERMAL RESPONSE, JUNCTION TO CASE
100
150oC
10
, FORWARD CURRENT (A)
F
I
1
012 3 45
V
VF, FORWARD VOLTAGE (V)
, FORWARD VOLTAGE (V)
F
25oC
FIGURE 17. DIODE FORWARDCURRENT vs FORWARD
VOLTAGE DROP
t
P
DUTY FACTOR, D = t1 / t
PEAK TJ = (PDX Z
-2
10
70
= 150oC
T
C
60
50
t
rr
40
t
30
t
20
t, RECOVERY TIMES (ns)
10
2
X R
θJC
10
) + T
θJC
C
-1
a
b
2
IF, FORWARD CURRENT (A)
D
0
10
5
FIGURE 18. RECOVERY TIMES vs FORWARD CURRENT
1
t
2
1
10
10
201
6
Page 7
Test Circuit and Waveforms
HGTG20N120C3D
HGTG20N120C3D
90%
V
GE
L = 1mH
RG = 3Ω
+
= 960V
V
DD
-
FIGURE 19. INDUCTIVE SWITCHING TEST CIRCUITFIGURE 20. SWITCHING TEST WAVEFORMS
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to gateinsulation damage by the electrostatic discharge of energy
through the devices. When handling these de vices , care
should be exercisedto assure that the static charge built in the
handler’s body capacitance is not discharged through the
device. With proper handling and application procedures,
howev er, IGBTs are currently being extensively used in
production by numerous equipment manufacturers in military,
industrial and consumer applications, with virtually no
damage problems due to electrostatic discharge. IGBTs can
be handled safely if the follo wing basic precautions are tak en:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs or by the insertion into conductive material such
as “ECCOSORBD™ LD26” or equivalent.
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
5. Gate Voltage Rating - Neverexceed the gate-voltage
rating of V
permanent damage to the oxide layer in the gate region.
6. Gate Termination - The gates of these devices are
essentially capacitors. Circuits that leave the gate opencircuited or floating should be avoided. These conditions
can result in turn-on of the device due to voltage buildup
on the input capacitor due to leakage currents or pickup.
7. Gate Protection- These devicesdo not havean internal
monolithic Zener diode from gate to emitter. If gate
. Exceeding the rated VGE can result in
GEM
V
CE
90%
I
CE
t
d(OFF)I
10%
Operating Frequency Information
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating device
performance for a specific application. Other typical
frequency vs collector current (I
the information shown for a typical unit in Figures 5, 6, 7, 8, 9
and 11. The operating frequency plot (Figure 3) of a typical
device shows f
point. The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
f
is defined by f
MAX1
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions
are possible. t
Device turn-off delay can establish an additional frequency
limiting condition for an application other than T
is important when controlling output ripple under a lightly
loaded condition.
f
is defined by f
MAX2
allowable dissipation (P
The sum of device switching and conduction losses must not
exceed P
. A 50% duty factor was used (Figure 3) and the
D
conduction losses (P
P
=(VCExICE)/2.
C
E
and E
ON2
OFF
shown in Figure 20. E
power loss (I
CE
integral of the instantaneous power loss (I
turn-off. All tail losses are included in the calculation forE
i.e., the collector current equals zero (I
or f
MAX1
MAX1
d(OFF)I
MAX2
C
are defined in the switching waveforms
x VCE) during turn-on and E
E
t
fI
MAX2
= 0.05/(t
and t
d(ON)I
= (PD - PC)/(E
) is defined by PD=(TJM-TC)/R
D
) are approximated by
is the integral of the instantaneous
ON2
E
ON2
OFF
) plots are possible using
CE
; whichever is smaller at each
d(OFF)I
are defined in Figure 20.
CE
protection is required an external Zener is recommended.
10%
t
rI
t
d(ON)I
+ t
d(ON)I
JM
+ E
OFF
ON2
is the
OFF
x VCE) during
CE
= 0).
).
. t
d(OFF)I
). The
θJC
OFF
.
;
7
ECCOSORBD‰ is a Trademark of Emerson and Cumming, Inc.
3. Add typically 0.002 inches (0.05mm) for solder coating.
4. Positionofleadtobe measured 0.250 inches(6.35mm)from bottom
of dimension D.
5. Positionofleadtobe measured 0.100 inches(2.54mm)from bottom
of dimension D.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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8
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