The HGTG20N100D2 is a MOS gated high voltage switching
device combining the best features of MOSFETs and bipolar
transistors. The device has the high input impedance of a MOSFET and the low on-state conduction loss of a bipolar transistor.
The much lower on-state voltage drop varies only moderately
between +25
IGBTs are ideal for many high voltage switching applications
operating at frequencies where low conduction losses are essential, such as: AC and DC motor controls, power supplies and
drivers for solenoids, relays and contactors.
Current Turn-On Delay Timet
Current Rise Timet
Current Turn-Off Delay Timet
Current Fall Timet
Turn-Off Energy (Note 1)W
Current Turn-On Delay Timet
Current Rise Timet
Current Turn-Offt
Current Fall Timet
Turn-Off Energy (Note 1)W
Thermal ResistanceR
NOTE: 1. T urn-Off Energy Loss (W
) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and
OFF
ending at the point where the collector current equals zero (ICE = 0A) The HGTG20N100D2 was tested per JEDEC standard No. 24-1
Method for Measurement of Power Device Turn-Off Switching Loss. This test method produces the true total T urn-Of f Energy Loss.
FIGURE 3. DC COLLECTOR CURRENT vs CASE TEMPERATUREFIGURE 4. FALL TIME vs COLLECTOR-EMITTER CURRENT
6000
5000
4000
C
ISS
3000
C
2000
C, CAPACITANCE (pF)
OSS
1000
C
RSS
0
0510152025
, COLLECTOR-TO-EMITTER VOLTAGE (V)
V
CE
f = 1MHz
1000
750
500
250
, COLLECTOR-EMITTER VOLTAGE (V)
CE
V
0
VCC = BV
CES
0.75 BV
0.50 BV
0.25 BV
GATEEMITTER
VOLTAGE
CES
CES
CES
COLLECTOR-EMITTER VOLTAGE
I
G(REF)
20
I
G(ACT)
TIME (µs)
I
0.75 BV
0.50 BV
0.25 BV
RL = 29Ω
G(REF)
V
GE
VCC = BV
CES
CES
CES
= 1.8mA
= 10V
CES
I
G(REF)
80
I
G(ACT)
10
5
0
FIGURE 5. CAPACITANCE vs COLLECT OR-EMITTER VOLTAGEFIGURE 6. NORMALIZED SWITCHING WAVEFORMS AT CON-
STANT GATE CURRENT (REFER TO APPLICATION
NOTES AN7254 AND AN7260)
, GATE-EMITTER VOLTAGE (V)
GE
V
5
TJ = +150oC
4
VGE = 10V
10
T
R
3
VGE = 15V
1.0
2
, SATURATION VOLTAGE (V)
1
CE(ON)
V
0
11040
, TURN-OFF SWITCHING LOSS (mJ)
OFF
W
0.1
11040
ICE, COLLECTOR-EMITTER CURRENT (A)
FIGURE 7. SATURATION VOLTAGE vs COLLECTOR-EMITTER
FIGURE 8. TURN-OFF SWITCHING LOSS vs COLLECTOR-
CURRENT
3-95
= +150oC, VGE = 15V,
J
= 25Ω, L = 50µH
G
VCE = 800V, VGE = 10V, 15V
= 400V, VGE = 10V, 15V
V
CE
, COLLECTOR-EMITTER CURRENT (A)
I
CE
EMITTER CURRENT
Page 4
HGTG20N100D2
Typical Performance Curves
1.2
= 15V, RG = 50Ω
V
GE
1.0
(Continued)
T
= +150oC
J
V
= 800V
CE
L = 50µH
VGE = 10V, RG = 50Ω
0.8
VGE = 15V, RG = 25Ω
0.6
VGE = 10V, RG = 25Ω
0.4
, TURN-OFF DELAY (µs)
D(OFF)I
t
0.2
0.0
11040
ICE, COLLECTOR-EMITTER CURRENT (A)
FIGURE 9. TURN-OFF DELAY vs COLLECTOR-EMITTER
CURRENT
40
VGE = 10V
10
TJ = +150oC
100
VCE = 400V
f
= 0.05/t
MAX1
f
MAX2
PC = DUTY FACTOR = 50%
R
θJC
10
, OPERATING FREQUENCY (kHz)
OP
f
TJ = +150oC, TC = +75oC, VGE = 15V
R
G
D(OFF)I
= (PD - PC)/W
= 0.7oC/W
= 25Ω, L = 50µH
OFF
V
= 800V
CE
1
110100
I
, COLLECTOR-EMITTER CURRENT (A)
NOTE:
CE
PD = ALLOWABLE DISSIPATION PC = CONDUCTION DISSIPATION
FIGURE 10. OPERATING FREQUENCY vs COLLECTOR-
EMITTER CURRENT AND VOLTAGE
Test Circuit
TJ = +25oC
, COLLECTOR-EMITTER CURRENT (A)
CE
I
1
12 3 4 5
V
, SATURATION VOLTAGE (V)
CE(ON)
FIGURE 11. COLLECTOR-EMITTER SATURATION VOLTAGE
L = 50µH
1/R
= 1/R
G
+ 1/R
GEN
R
GEN
= 50Ω
GE
V
CC
800V
+
-
20V
0V
RGE = 50Ω
FIGURE 12. INDUCTIVE SWITCHING TEST CIRCUIT
3-96
Page 5
Operating Frequency Information
HGTG20N100D2
Operating frequency information for a typical device (Figure
10) is presented as a guide for estimating device performance
for a specific application. Other typical frequency vs collector
current (I
) plots are possible using the information shown
CE
for a typical unit in Figures 7, 8 and 9. The operating
frequency plot (Figure 10) of a typical device shows f
f
whichever is smaller at each point. The information is
MAX2
MAX1
or
based on measurements of a typical device and is bounded
by the maximum rated junction temperature.
f
is defined by f
MAX1
MAX1
= 0.05/t
D(OFF)I
. t
D(OFF)I
deadtime
(the denominator) has been arbitrarily held to 10% of the onstate time for a 50% duty factor. Other definitions are possible.
t
is defined as the time between the 90% point of the
D(OFF)I
trailing edge of the input pulse and the point where the
collector current falls to 90% of its maximum value. Device
turn-off delay can establish an additional frequency limiting
condition for an application other than T
JMAX
. t
D(OFF)I
is
important when controlling output ripple under a lightly loaded
condition.
f
is defined by f
MAX2
dissipation (P
) is defined by PD = (T
D
= (PD - PC)/W
MAX2
JMAX
. The allowable
OFF
- TC)/R
θJC
. The sum
of device switching and conduction losses must not exceed P
A 50% duty factor was used (Figure 10) and the conduction
losses (P
) are approximated by PC = (VCE • ICE)/2. W
C
OFF
is
defined as the integral of the instantaneous power loss starting
at the trailing edge of the input pulse and ending at the point
where the collector current equals zero (I
The switching power loss (Figure 10) is defined as f
W
. Turn-on switching losses are not included because they
OFF
CE
= 0A).
MAX2
can be greatly influenced by external circuit conditions and components.
.
D
•
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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