600V, SMPS Series N-Channel IGBT with
Anti-Parallel Hyperfast Diode
The HGT1S3N60A4DS and the HGTP3N60A4D are MOS
gated high voltage switching devices combining the best
featuresof MOSFETs and bipolar transistors. These devices
have the high input impedance of a MOSFET and the low
on-state conduction loss of a bipolar transistor. The much
lower on-state voltage drop varies only moderately between
o
25
C and 150oC. The IGBT used is the development type
TA49327. The diode used in anti-parallel is the development
type TA49369.
This IGBT is ideal for many high voltage switching
applications operating at high frequencies where low
conduction losses are essential. This device has been
optimized for high frequency switch mode power
supplies.
Formerly Developmental Type TA49329.
Ordering Information
File Number4818
Features
• >100kHz Operation At 390V, 3A
• 200kHz Operation At 390V, 2.5A
• 600V Switching SOA Capability
• Typical Fall Time. . . . . . . . . . . . . . . . . 70ns at T
• Low Conduction Loss
• Temperature Compensating SABER™ Model
www.intersil.com
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
PKG
300
260
o
C
o
C
o
C
NOTE:
1. Pulse width limited by maximum junction temperature.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
J
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Collector to Emitter Breakdown VoltageBV
Collector to Emitter Leakage CurrentI
2. Valuesfor two Turn-On loss conditions are shown fortheconvenienceof the circuit designer. E
is the turn-on loss of the IGBT only.E
ON1
is the turn-on loss when a typical diode is used in the test circuit and the diode is at the same TJas the IGBT. The diode type is specified in
Figure 24.
3. Turn-Off Energy Loss (E
) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and
OFF
ending at the point where the collector current equals zero (ICE = 0A). All devices were tested per JEDEC Standard No. 24-1 Method for
Measurement of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss.
FIGURE 23. IGBT NORMALIZED TRANSIENT THERMAL RESPONSE, JUNCTION TO CASE
Test Circuit and Waveforms
V
HGTP3N60A4D
DIODE TA49369
L = 1mH
RG = 50Ω
DUT
+
= 390V
V
DD
-
FIGURE 24. INDUCTIVE SWITCHING TEST CIRCUITFIGURE 25. SWITCHING TEST WAVEFORMS
7
GE
I
CE
V
CE
t
d(OFF)I
90%
E
OFF
90%
10%
t
fI
E
10%
0N2
t
d(ON)I
I
CE
t
rI
Page 8
HGT1S3N60A4DS, HGTP3N60A4D
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to
gate-insulation damage by the electrostatic discharge of
energy through the devices. When handling these devices,
care should be exercised to assure that the static charge
built in the handler’s body capacitance is not discharged
through the device. With proper handling and application
procedures, however, IGBTs are currently being extensively
used in production by numerous equipment manufacturers in
military, industrial and consumer applications, with virtually
no damage problems due to electrostatic discharge. IGBTs
can be handled safely if the following basic precautions are
taken:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs or by the insertion into conductive material such
as “ECCOSORBD™ LD26” or equivalent.
2. When devicesare removed by hand from their carriers,
the hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should neverbe inserted into or removedfrom
circuits with power on.
5. Gate Voltage Rating - Neverexceedthe gate-voltage
rating of V
permanent damage to the oxide layer in the gate region.
6. Gate Termination - The gates of these devices are
essentially capacitors. Circuits that leave the gate
open-circuited or floating should be avoided. These
conditions can result in turn-on of the device due to
voltage buildup on the input capacitor due to leakage
currents or pickup.
7. Gate Protection - These devicesdonothaveaninternal
monolithic Zener diode from gate to emitter. If gate
protection is required an external Zener is recommended.
. Exceeding the rated VGE can result in
GEM
Operating Frequency Information
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating device
performance for a specific application. Other typical
frequency vs collector current (I
the information shown for a typical unit in Figures 6, 7, 8, 9
and 11. The operating frequency plot (Figure 3) of a typical
device shows f
MAX1
or f
MAX2
point. The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
f
is defined by f
MAX1
MAX1
= 0.05/(t
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions
are possible. t
d(OFF)I
and t
d(ON)I
Device turn-off delay can establish an additional frequency
limiting condition for an application other than T
is important when controlling output ripple under a lightly
loaded condition.
f
is defined by f
MAX2
allowable dissipation (P
= (PD - PC)/(E
MAX2
) is defined by PD=(TJM-TC)/R
D
The sum of device switching and conduction losses must not
exceed P
conduction losses (P
P
C
E
ON2
shown in Figure 25. E
. A 50% duty factor was used (Figure 3) and the
D
) are approximated by:
C
=(VCExICE)/2.
and E
are defined in the switching waveforms
OFF
is the integral of the
ON2
instantaneous power loss (I
E
is the integral of the instantaneous power loss
OFF
(I
CExVCE
calculation for E
(I
CE
) during turn-off. All tail losses are included in the
; i.e., the collector current equals zero
OFF
= 0).
) plots are possible using
CE
; whichever is smaller at each
d(OFF)I
+ t
d(ON)I
).
are defined in Figure 25.
. t
JM
d(OFF)I
+ E
OFF
x VCE) during turn-on and
CE
ON2
). The
θJC
.
8
ECCOSORBD™ is a trademark of Emerson and Cumming, Inc.
Page 9
HGT1S3N60A4DS, HGTP3N60A4D
TO-263ABSURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-263AB outline dated 2-92.
2. L3and b2dimensions established a minimum mounting surface
for terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Positionoflead tobe measured 0.120inches (3.05mm)frombottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 11 dated 5-99.
TO-263AB
24mm TAPE AND REEL
1.5mm
DIA. HOLE
24mm
GENERAL INFORMATION
1. 800 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
USER DIRECTION OF FEED
COVER TAPE
4.0mm
16mm
2.0mm
40mm MIN.
ACCESS HOLE
330mm
1.75mm
C
L
30.4mm
13mm
100mm
24.4mm
9
Page 10
HGT1S3N60A4DS, HGTP3N60A4D
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
ØP
Q
D
E
1
L
1
E
H
1
D
1
b
1
A
A
1
SYMBOL
A0.1700.1804.324.57-
A
1
TERM. 4
o
45
b0.0300.0340.770.863, 4
b
1
c0.0140.0190.360.482, 3 , 4
D0.5900.61014.9915.49-
D
1
INCHESMILLIMETERS
NOTESMINMAXMINMAX
0.0480.0521.221.32-
0.0450.0551.151.392, 3
-0.160-4.06-
E0.3950.41010.0410.41-
L
o
60
1
e
1
b
c
E
1
-0.030-0.76-
e0.100 TYP2.54 TYP5
3
2
e
J
1
e
1
H
1
J
1
0.200 BSC5.08 BSC5
0.2350.2555.976.47-
0.1000.1102.542.796
L0.5300.55013.4713.97-
L
1
0.1300.1503.313.812
ØP0.1490.1533.793.88-
Q0.1020.1122.602.84-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured0.250inches(6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured0.100inches(2.54mm) from bot-
tom of dimension D.
7. Controlling dimension: Inch.
8. Revision 2 dated 7-97.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
10
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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