Datasheet HG74ALVC16835C Datasheet (HEI)

18-BIT UNIVERSAL BUS DRIVER HG74ALVC16835C

WITH 3-STATE OUTPUTS Jan 1999

Features

l Ideal for Use in PC100 Registered DIMM
l 0.5µm CMOS Technology

l 2.3 ~ 3.6 V

Operation

CC

l Balanced Output Drive(±24mA)
l Package Options Include Plastic Thin

Shrink Small-Outline Packages, Shrink
Small-Outline Packages
(TSSOP 56 Pins, SSOP 56 Pins, TVSOP56 Pins)

Pin Configuration

(TOP VIEW)

NC
NC

Y1

GND

Y2
Y3

Vcc

Y4
Y5
Y6

GND

Y7
Y8

Y9
Y10
Y11
Y12

GND

Y13
Y14
Y15
Vcc
Y16
Y17

GND

Y18

OE

LE

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56

GND

55

NC

54

A1

53

GND

52

A2

51

A3

50

Vcc

49

A4

48

A5

47

A6

46

GND

45

A7

44

A8

43

A9

42

A10

41

A11

40

A12

39

GND

38

A13

37

A14

36

A15

35

Vcc

34

A16

33

A17

32

GND

31

A18

30

CLK

29

GND

General Description

The HG74ALVC16835C is an 18-bit universal bus
driver designed for 2.3V to 3.6 V V

The Output-Enable(OE) controls data flow from A to Y.
The device operates in transparent mode when the
latch-enable(LE) input is high. When LE is low, the A
data is latched if the clock input is held at a high or low
logic level.
If LE is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK.

When OE is high, the Outputs are in the high
impedance state. OE should be tied to V
pull up resistor to ensure the high impedance state
during power up or power down.

The HG74ALVC16835C is characterized for operation
from -40°C to 85°C.

Function Table

INPUTS

OE

H X X X Z
L H X L L
L H X H H
L L
L L
L L L or H X Y

=Output level before the indicated steady-state input

conditions were established, provided that CLK is high
before LE goes low.

LE CLK A

↑
↑

L L
H H

Operation.

CC

CC

OUTPUT
Y

=

O

through a

NC- No ineternal connection

1

Copyright©1999, Hyundai Electronics Industries Co., Ltd.

ELECTRONICS

18-BIT UNIVERSAL BUS DRIVER HG74ALVC16835C

WITH 3-STATE OUTPUTS Jan 1999

Logic Diagram (positive logic)

27

OE

30

CLK

28

LE

54

A1 Y1

TO 17 Other Channels

1D
C1
CLK

Absolute Maximum Ratings Over Operating Free-air Temperature Range

3

=

Symbols Parameter Value Conditions

V

CC

V

I

V

O

I

IK

I

OK

I

O

I

CC

I

GND

T

stg

=Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition” is not
implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

Supply Voltage Range -0.5 V to 4.6 V
Input Voltage Range (see note 1)
Output Voltage Range (see note 1 and 2)
Input Clamp Current
Output Clamp Current
Continuous Output Current
Continuous Current through each V

CC

-0.5V to VCC+

-0.5V to VCC+

±50 mA
±50 mA

± 50 mA

+100 mA

0.5V

0.5V

Continuous Current through each GND -100 mA
Storage Temperature Range

-65°C to 150°C

VI < 0

VO <0 or VO >V

VO =0 to V

CC

CC

Note 1) The input and output voltage ratings may be exceeded if the input and output clamp current are observed.
Note 2) This value is limited to 4.6 V maximum.

Copyright©1999, Hyundai Electronics Industries Co., Ltd.

ELECTRONICS

2

18-BIT UNIVERSAL BUS DRIVER HG74ALVC16835C

WITH 3-STATE OUTPUTS Jan 1999

Recommended Operating Conditions (see Note 3)

Symbols Parameter

V

CC

V

IH

V

IL

V

I

V

O

OH

I

OL

∆t/∆v

T

A

Note 3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation.

Supply Voltage 2.3 3.6 V
High -level input Voltage

Low-level input Voltage
Input Voltage 0 V

Output Voltage 0 V
High-level output current

Low-level output current
Input transition rise or fall rate 0 10 ns/V

Operating free-air temperature -40 85

Value

MIN MAX

Units Conditions

1.7 V VCC =2.3V to 2.7V
2 V VCC =2.7V to 3.6V

0.7 V VCC =2.3V to 2.7V

0.8 V VCC =2.7V to 3.6V

CC
CC

V
V

-12 mA VCC =2.3V

-12 mA VCC =2.7VI

-24 mA VCC =3V
12 mA VCC =2.3V
12 mA VCC =2.7V
24 mA VCC =3V

°C

Electrical Characteristics Over Recommended Operating Free-air Temperature Range

Value

Parameter Test Conditions

IOH = -100µA VCC−
IOH = - 6mA VIH =1.7V 2 2.3V

V

OH

IOH = -12mA

IOH = -24 mA VIH = 2V 2
IOL = 100µA
IOL = 6mA VIL = 0.7V 0.4 2.3V

V

OL

IOL =24mA VIL = 0.8V 0.55

I
∆I

I

L

I

OZ

CC

CC

VI= VCC or GND
VO = VCC or GND
VI = VCC or GND

IO = 0
One input at VCC - 0.6V,
Other inputs at VCC or GND

Control Inputs

C

I

C

o

=

All typical Values are at VCC =3.3V, TA = 25°C.

Data Inputs

Outputs VO= VCC or GND

VI = VCC or GND

Min Typ= Max

0.2

VIH =1.7V 1.7 2.3V
VIH = 2V

2.2 2.7V

2.4 3V

0.2 2.3V to 3.6V

VIL = 0.7V 0.7 2.3VIOL = 12mA
VIL = 0.8V 0.4 2.7V

±5

±10

40 3.6V

750

3.5
5

7

Units V

2.3V to 3.6V

V

3V

V

3V

3.6V

3.6V

µA

3V to 3.6V

ρF

ρF

3.3V

3.3V

CC

3

Copyright©1999, Hyundai Electronics Industries Co., Ltd.

ELECTRONICS

18-BIT UNIVERSAL BUS DRIVER HG74ALVC16835C

WITH 3-STATE OUTPUTS Jan 1999

Timing Requirements Over Recommended Operating Free-air Temperature Range(see figure1~10 )

Symbol Parameter

Condition

Vcc=2.5V±0.2V

Vcc=2.7V

Vcc=3.3V±0.3V

Min Max Min Max Min Max

W

su

Clock
frequency
Pulse
Duration

Setup time

150 150 150 MHz

LE high 3.3 3.3 3.3 ns

CLK high or low 3.3 3.3 3.3 ns

Data before CLK↑

Data before LE↓

CLK high 1.9 1.6 1.5 ns

0.9 0.9 0.7 ns

f

clock

t

t

CLK low 1.3 1.1 1 ns

1.0 1.0 1.1 ns

1.4 1.7 1.4 ns

t

h

Hold time

Data after CLK↑

Data after LE↓

CLK high

or low

Switching Characteristics Over Recommended Operating Free-air Temperature Range

V

Parameter

f

max

pd

t

en

I

dis

Input

(From)

Output

(to)

V

=2.5V± 0.2V

CC

Min Max Min Max Min Max
150 150 150 MHz

A 1 4.2 4.2 1 3.6 ns

LE 1.3 5 4.9 1.3 4.2 nst

CLK

Y 1.4 5.5 5.6 1.1 4.6 ns

OE

Y 1 4.5 4.3 1.3 3.9 ns

OE

Y

1.4 5.5 5.2 1.4 4.5 ns

=2.7V

CC

V

=3.3V±0.3V

CC

Unit

Unit

Switching Characteristics From 0°C to 65°C, CL=50ρF

Parameter Input

(From)

t

pd

CLK Y 1.7 4.5 ns

Output

(To)

Parameter Measurement (VCC=2.5V±0.2V)

500

Ω

From Output

Under Test

CL= 30pF

(

see Note)

Ω

500

Figure 1. Load Circuit

VCC=3.3V± 0.15V

Min Max

2 x Vcc

S1

Open

GND

Test S1

t

pd

t

/ t

PLZ

PZL

t

/t

PHZ

PZH

Unit

Open

2 x V

GND

CC

Note) CL includes probe and jig capacitance

Copyright©1999, Hyundai Electronics Industries Co., Ltd.

ELECTRONICS

4

18-BIT UNIVERSAL BUS DRIVER HG74ALVC16835C

WITH 3-STATE OUTPUTS Jan 1999

Voltage Waveforms

V

0V

V
0V

CC

t

w

CC

Input

VCC /2

VCC /2

Timing
Input

Data
Input

t

su

VCC /2

VCC /2

t

h

VCC /2

V

0V

CC

Figure 2. Set up and Hold Times

Output

Output Control
(Low-level enabling)

Output Waveform 1
S1 at 2 x V
(See Note 1 )

Input

CC

Figure 3. Pulse Duration

V

CC

VCC /2

VCC /2

0V

t

t

PLH

VCC/2

PHL

VCC /2

V

V

OH

OL

Figure 4. Propagation Delay times

V

0V

V

V

OL

CC

CC

VCC /2

t

PZL

VCC /2

VCC /2

t

PLZ

VOL + 0.15V

t

Output Waveform 2
S1 at GND

PZH

VCC /2

t

PHZ

VOH - 0.15V

V

0V

OH

(See Note 1 )

Figure 5. Enable and Disable Times

Note 1 )Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control
Note 2) All input pulses are supplied by generators having the following characteristics:
PRR ⊆ 10Mhz, Zo = 50Ω , tr ⊆ 2ns, tf ⊆ 2ns.
Note 3) The output are measured one at a time with one transition per measurement.
Note 4) t
Note 5) t
Note 6) t

PLZ
PZL
PLH

and t

are the same as t

PHZ

and t

are the same as ten .

PZH

and t

are the same as tpd.

PHL

.

dis

5

Copyright©1999, Hyundai Electronics Industries Co., Ltd.

ELECTRONICS

18-BIT UNIVERSAL BUS DRIVER HG74ALVC16835C

S1

Open
GND

WITH 3-STATE OUTPUTS Jan 1999

Parameter Measurement (Vcc=2.7V and 3.3V±0.3V)

From Output

500

Under Test

C

= 50pF

L

(see note)

500

Figure 6. Load Circuit

Note) CL includes probe and jig capacitance

Voltage Waveforms

Timing
Input

Data
Input

t

su

1.5V

t

1.5V

h

1.5V

2.7V

0V

2.7V
0V

6V

Input

Test S1

t

pd

t

/ t

PLZ

t

/t

PHZ

PZH

t

w

1.5V

PZL

Open

6V

GND

2.7V

1.5V

0V

Figure 7. Set up and Hold Times

1.5V

Input

Output

1.5V

t

PLH

1.5V

Figure 9. Propagation Delay times

Copyright©1999, Hyundai Electronics Industries Co., Ltd.

ELECTRONICS

Figure 8. Pulse Duration

2.7V

0V

t

PHL

V

V

OH

OL

1.5V

6

18-BIT UNIVERSAL BUS DRIVER HG74ALVC16835C

Output Control

Output Waveform 1

Output Waveform 2

WITH 3-STATE OUTPUTS Jan 1999

(Low-level enabling)

1.5V

2.7V

0V

t

PLZ

VCC + 0.3V

t

PHZ

V

- 0.3V

OH

3V

V

V

0V

OL

OH

S1 at 6V
(See Note1)

S1 at GND
(See Note1)

t

PZL

1.5V

t

PZH

1.5V

Figure 10. Enable and Disable Times

Note 1 ) Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control
Note 2) All input pulses are supplied by generators having the following characteristics :
PRR ⊆ 10MHz, Zo = 50Ω, tr ⊆ 2.5ns, tf ⊆ 2.5ns.
Note 3) The output are measured one at a time with one transition per measurement.
Note 4) t
Note 5) t
Note 6) t

PLZ
PZL
PLH

and t

are the same as t

PHZ

and t

are the same as ten .

PZH

and t

are the same as tpd.

PHL

.

dis

7

Copyright©1999, Hyundai Electronics Industries Co., Ltd.

ELECTRONICS