Page 1
HFA1405
September 1998 File Number 3604.5
Quad, 560MHz, Low Power, Video
Operational Amplifier
The HFA1405 is a quad, high speed, low power current
feedback amplifier built with Intersil’s proprietary
complementary bipolar UHF-1 process.
These amplifiers deliver up to 560MHz bandwidth and
1700V/µs slew rate,ononly58mWofquiescentpower.They
are specifically designed to meet the performance, power,
and cost requirements of high volume video applications.
The excellent gain flatness and differential gain/phase
performance make these amplifiers well suited for
component or composite video applications. Video
performance is maintained even when driving a back
terminated cable (R
when driving two back terminated cables (R
= 150Ω), and degrades only slightly
L
= 75Ω). RGB
L
applications will benefit from the high slew rates, and high
full power bandwidth.
The HFA1405 is a pin compatible, low power, high
performance upgrade for the popular Intersil HA5025, and
for the CLC414 and CLC415.
Ordering Information
TEMP.
PART NUMBER
HFA1405IB -40 to 85 14 Ld SOIC M14.15
HFA1405IP -40 to 85 14 Ld PDIP E14.3
HA5025EVAL High Speed Op Amp DIP Evaluation Board
RANGE (oC) PACKAGE
PKG.
NO.
Pinout
HFA1405
(PDIP, SOIC)
TOP VIEW
Features
• Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA/Op Amp
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ
• Wide -3dB Bandwidth (A
= +2). . . . . . . . . . . . . . 560MHz
V
• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1700V/µs
• Gain Flatness (to 50MHz). . . . . . . . . . . . . . . . . . . . ±0.03dB
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Differential Phase. . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• All Hostile Crosstalk (5MHz). . . . . . . . . . . . . . . . . . -60dB
• Pin Compatible Upgrade to HA5025, CLC414, and
CLC415
Applications
• Flash A/D Drivers
• Professional Video Processing
• Video Digitizing Boards/Systems
• Multimedia Systems
• RGB Preamps
• Medical Imaging
• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications
• High Speed Oscilloscopes and Analyzers
OUT 1
-IN 1
+IN 1
V+
+IN 2
-IN 2
OUT 2
1
2
-
+
3
4
5
+
-
6
7
14
OUT 4
13
-IN 4
-
+
12
+IN 4
11
V-
10
+IN 3
+
-
9
-IN 3
8
OUT 3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Page 2
HFA1405
Absolute Maximum Ratings T
Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current (Note 2). . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . 600V
=25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SUPPLY
30mA Continuous
60mA ≤ 50% Duty Cycle
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Output is shortcircuit protected toground.Brief short circuitstoground will notdegrade reliability, howevercontinuous(100% duty cycle)output
current must not exceed 30mA for maximum reliability.
Electrical Specifications V
PARAMETER TEST CONDITIONS
INPUT CHARACTERISTICS
Input Offset Voltage A 25 - 2 5 - 2 5 mV
Average Input Offset Voltage Drift B Full - 1 10 - 1 10 µV/oC
Input Offset Voltage
Common-Mode Rejection Ratio
Input Offset Voltage
Power Supply Rejection Ratio
Non-Inverting Input Bias Current A 25 - 6 15 - 6 15 µA
Non-Inverting Input Bias Current
Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity
Non-Inverting Input Resistance ∆VCM= ±1.8V A 25 0.8 1.2 - 0.8 1.2 - MΩ
Inverting Input Bias Current A 25 - 2 7.5 - 2 7.5 µA
Inverting Input Bias Current Drift B Full - 60 200 - 60 200 nA/oC
Inverting Input Bias Current
Common-Mode Sensitivity
= ±5V, AV= +1, RF= 510Ω, RL = 100Ω, Unless Otherwise Specified
SUPPLY
(NOTE 4)
TEST
LEVEL
∆VCM= ±1.8V A 25 45 48 - 45 48 - dB
∆VCM= ±1.8V A 85 43 46 - 43 46 - dB
∆VCM= ±1.2V A -40 43 46 - 43 46 - dB
∆VPS= ±1.8V A 25 48 52 - 48 52 - dB
∆VPS= ±1.8V A 85 46 48 - 46 48 - dB
∆VPS= ±1.2V A -40 46 48 - 46 48 - dB
∆VPS= ±1.8V A 25 - 0.5 1 - 0.5 1 µA/V
∆VPS= ±1.8V A 85 - 0.8 3 - 0.8 3 µA/V
∆VPS= ±1.2V A -40 - 0.8 3 - 0.8 3 µA/V
∆VCM= ±1.8V A 85 0.5 0.8 - 0.5 0.8 - MΩ
∆VCM= ±1.2V A -40 0.5 0.8 - 0.5 0.8 - MΩ
∆VCM= ±1.8V A 25 - 3 6 - 3 6 µA/V
∆VCM= ±1.8V A 85 - 4 8 - 4 8 µA/V
∆VCM= ±1.2V A -40 - 4 8 - 4 8 µA/V
TEMP.
(oC)
A Full - 3 8 - 3 8 mV
A Full - 10 25 - 10 25 µA
B Full - 5 60 - 5 60 nA/oC
A Full - 5 15 - 5 15 µA
HFA1405IB (SOIC) HFA1405IP (PDIP)
UNITSMIN TYP MAX MIN TYP MAX
2
Page 3
HFA1405
Electrical Specifications V
PARAMETER TEST CONDITIONS
Inverting Input Bias Current
Power Supply Sensitivity
= ±5V, AV= +1, RF= 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
(NOTE 4)
TEST
LEVEL
TEMP.
(oC)
HFA1405IB (SOIC) HFA1405IP (PDIP)
∆VPS= ±1.8V A 25 - 2 5 - 2 5 µA/V
∆VPS= ±1.8V A 85 - 4 8 - 4 8 µA/V
UNITSMIN TYP MAX MIN TYP MAX
∆VPS= ±1.2V A -40 - 4 8 - 4 8 µA/V
Inverting Input Resistance C 25 - 60 - - 60 - Ω
Input Capacitance B 25 - 1.4 - - 2.2 - pF
Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN, and
-I
CMS Tests)
B-IAS
A 25, 85 ±1.8 ±2.4 - ±1.8 ±2.4 - V
A -40 ±1.2 ±1.7 - ±1.2 ±1.7 - V
Input Noise Voltage Density f = 100kHz B 25 - 3.5 - - 3.5 - nV/√Hz
Non-Inverting Input Noise Current
f = 100kHz B 25 - 2.5 - - 2.5 - pA/√Hz
Density
Inverting Input Noise Current Density f = 100kHz B 25 - 20 - - 20 - pA/√Hz
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain AV= -1 C 25 - 500 - - 500 - kΩ
AC CHARACTERISTICS (Note 3)
-3dB Bandwidth
(V
= 0.2V
OUT
, Notes 3, 5)
P-P
AV= -1 B 25 - 420 - - 360 - MHz
AV= +2 B 25 - 560 - - 400 - MHz
AV= +6 B 25 - 140 - - 100 - MHz
Full Power Bandwidth
(V
=5V
OUT
, Notes 3, 5)
P-P
AV= -1 B 25 - 260 - - 260 - MHz
AV= +2 B 25 - 165 - - 165 - MHz
AV= +6 B 25 - 140 - - 100 - MHz
Gain Flatness
(V
= 0.2V
OUT
, Notes 3, 5)
P-P
AV= -1, To 25MHz B 25 - ±0.03 - - ±0.04 - dB
AV= -1, To 50MHz B 25 - ±0.04 - - ±0.04 - dB
AV= -1, To 100MHz B 25 ----±0.06 - dB
AV= +2, To 25MHz B 25 - ±0.03 - - ±0.04 - dB
AV= +2, To 50MHz B 25 - ±0.03 - - ±0.04 - dB
AV= +2, To 100MHz B 25 ----±0.06 - dB
AV= +6, To 15MHz B 25 - ±0.08 - - ±0.08 - dB
AV= +6, To 30MHz B 25 - ±0.19 - - ±0.27 - dB
Minimum Stable Gain A Full - 1 - - 1 - V/V
Crosstalk
(AV= +2, All Channels Hostile,
Note 5)
5MHz B 25 - -60 - - -55 - dB
10MHz B 25 - -56 - - -52 - dB
OUTPUT CHARACTERISTICS AV= +2 (Note 3), Unless Otherwise Specified
Output Voltage Swing
(Note 5)
Output Current
(Note 5)
AV= -1, RL= 100Ω A25±3 ±3.4 - ±3 ±3.4 - V
A Full ±2.8 ±3-±2.8 ±3- V
AV= -1, RL=50Ω A 25, 85 50 60 - 50 60 - mA
A -40 28 42 - 28 42 - mA
Output Short Circuit Current B 25 - 90 - - 90 - mA
Closed Loop Output Impedance B 25 - 0.2 - - 0.2 - Ω
Second Harmonic Distortion
(V
=2V
OUT
P-P
, Note 5)
10MHz B 25 - -51 - - -51 - dBc
20MHz B 25 - -46 - - -46 - dBc
3
Page 4
HFA1405
Electrical Specifications V
PARAMETER TEST CONDITIONS
Third Harmonic Distortion
(V
=2V
OUT
P-P
, Note 5)
= ±5V, AV= +1, RF= 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
(NOTE 4)
TEST
LEVEL
TEMP.
(oC)
HFA1405IB (SOIC) HFA1405IP (PDIP)
10MHz B 25 - -63 - - -63 - dBc
20MHz B 25 - -56 - - -56 - dBc
UNITSMIN TYP MAX MIN TYP MAX
TRANSIENT CHARACTERISTICS AV= +2 (Note 3), Unless Otherwise Specified
Rise and Fall Times
(V
OUT
= 0.5V
P-P
, Note 3)
Overshoot
(V
OUT
= 0.5V
P-P
, VIN t
Notes 3, 6)
RISE
= 1ns,
AV= +2 B 25 - 0.8 - - 0.9 - ns
AV= +6 B 25 - 2.9 - - 4 - ns
AV= -1, +OS B 25 - 7 - - 3 - %
AV= -1, -OS B 25 - 8 - - 13 - %
AV= +2, +OS B 25 - 5 - - 7 - %
AV= +2, -OS B 25 - 10 - - 11 - %
AV= +6, +OS B 25 - 2 - - 2 - %
AV= +6, -OS B 25 - 2 - - 2 - %
Slew Rate
(V
=5V
OUT
, Notes 3, 5)
P-P
AV= -1, +SR B 25 - 2500 - - 2500 - V/µs
AV= -1, -SR B 25 - 1900 - - 1900 - V/µs
AV= +2, +SR B 25 - 1700 - - 1600 - V/µs
AV= +2, -SR B 25 - 1700 - - 1400 - V/µs
AV= +6, +SR B 25 - 1500 - - 1000 - V/µs
AV= +6, -SR B 25 - 1100 - - 1000 - V/µs
Settling Time
(V
= +2V to 0V Step, Note 5)
OUT
To 0.1% B 25 - 23 - - 23 - ns
To 0.05% B 25 - 30 - - 30 - ns
To 0.025% B 25 - 37 - - 40 - ns
Overdrive Recovery Time VIN= ±2V B 25 - 8.5 - - 8.5 - ns
VIDEO CHARACTERISTICS AV= +2 (Note 3), Unless Otherwise Specified
Differential Gain
(f = 3.58MHz)
Differential Phase
(f = 3.58MHz)
RL= 150Ω B 25 - 0.02 - - 0.03 - %
RL=75Ω B 25 - 0.03 - - 0.06 - %
RL= 150Ω B 25 - 0.03 - - 0.03 - Degrees
RL=75Ω B 25 - 0.06 - - 0.06 - Degrees
POWER SUPPLY CHARACTERISTICS
Power Supply Range C 25 ±4.5 - ±5.5 ±4.5 - ±5.5 V
Power Supply Current (Note 5) A 25 - 5.8 6.1 - 5.8 6.1 mA/Op
Amp
A Full - 5.9 6.3 - 5.9 6.3 mA/Op
Amp
NOTES:
3. The optimum feedback resistor depends on closed loop gain and package type. The following resistors were used for the PDIP/SOIC characterization: AV= -1, RF= 310Ω/360Ω; AV= +2, RF= 402Ω/510Ω; AV= +6, RF= 500Ω/500Ω. See the Application Information section for more
information.
4. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
5. See Typical Performance Curves for more information.
6. Undershoot dominates for output signal swings below GND (e.g., 2V
), yielding a higher overshoot limit compared to the V
P-P
OUT
=0Vto2V
condition. See the “Application Information” section for details.
4
Page 5
HFA1405
Application Information
Performance Differences Between PDIP and SOIC
The amplifiers comprising the HFA1405 are high frequency
current feedback amplifiers. As such, they are sensitive to
feedback capacitance which destabilizes the op amp and
causes overshoot and peaking. Unfortunately, the standard
quad op amp pinout places the amplifier’s output next to its
inverting input, thus making the package capacitance an
unavoidable parasitic feedback capacitor. The larger
parasitic capacitance of the PDIP requires an inherently
more stable amplifier, which yields a PDIP device with lower
performance than the SOIC device - see Electrical
Specification tables for details.
Because of these performance differences, designers
should evaluate and breadboard with the same package
style to be used in production.
Note that the “Typical Performance Curves” section has
separate pulse and frequency response graphs for each
package type. Graphs not labeled with a specific package
type are applicable to both packages.
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and R
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and R
, in conjunction with
F
the internal compensation capacitor, sets the dominant pole
of the frequencyresponse.Thus,theamplifier’s bandwidth is
inversely proportional to R
optimized for R
Decreasing R
= 402Ω/510Ω (PDIP/SOIC) at a gain of +2.
F
decreases stability, resulting in excessive
F
. The HFA1405 design is
F
peaking and overshoot (Note: Capacitive feedback causes
the same problems due to the feedback impedance
decrease at higher frequencies). However, at higher gains
the amplifier is more stable so R
can be decreased in a
F
trade-off of stability for bandwidth.
The table below lists recommended R
values for various
F
gains, and the expected bandwidth. For good channel-tochannel gain matching, it is recommended that all resistors
(termination as well as gain setting) be ±1% tolerance or
better.
OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL)
-1 310/360 360/420
+2 402/510 400/560
+6 500/500 (Note) 100/140
RF (Ω)
PDIP/SOIC
BANDWIDTH (MHz)
PDIP/SOIC
.
F
NOTE: RF= 500Ω is not the optimum value. It was chosen to
match the RFof the CLC414 and CLC415, for performance comparison purposes. Performance at AV= +6 may be increased by reducing RF below 500Ω.
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be ≥ 50Ω. This is especially
important in inverting gain configurations where the noninverting input would normally be connected directly to GND.
Pulse Undershoot
The HF A1405 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor . The composite de vice
switches modes after crossing 0V, resulting in added distortion
for signals swinging belo w ground, and an increased
undershoot onthenegative portion oftheoutputwaveform(see
Figure 6 and Figure 9). This undershoot isn’t present for small
bipolar signals, or large positive signals (see Figure 5 and
Figure 8).
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance, parasitic or
planned, connected to the output must be minimized, or
isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance,theworsethegain peaking, resulting
in pulse overshoot and eventual instability. To reduce this
capacitance the designer should remove the ground plane
under traces connected to -IN, and keep connections to -IN
as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
prior to the capacitance.
) in series with the output
S
5
Page 6
HFA1405
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
and C
S
L
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdampedresponse,whilepointsbelow or left of the curve
indicate areas of underdamped performance.
R
and CLform a lowpassnetworkattheoutput,thuslimiting
S
system bandwidth well below the amplifier bandwidth of
560MHz. By decreasing R
as CL increases (as illustrated in
S
the curve), the maximum bandwidth is obtained without
sacrificing stability . In spite of this, bandwidth still decreases
as the load capacitance increases.
50
40
30
20
A
=+2
10
SERIES OUTPUT RESISTANCE (Ω)
V
R
S
50Ω
OUT
R
IN
50Ω
+5V
10µF 0.1µF
G
1
R
F
2
+
3
4
5
6
7
14
13
12
11
10
9
8
FIGURE 2. EVALUATION BOARD SCHEMATIC
TOP LAYOUT
-5V
0.1µF10µF
GND
GND
0
0 100 200 300 400
150 250 35050
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES OUTPUTRESISTOR vs
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1405 (PDIP) may be evaluated
using the HA5025 Evaluation Board.
The schematic for amplifier 1 and the board layout are
shown in Figure 2 and Figure 3. Resistors R
may require a change to values applicable to the HFA1405.
To order evaluation boards (part number HA5025EVAL),
please contact your local sales office.
, RG, and R
F
S
BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
6
Page 7
HFA1405
Typical Performance Curves
160
AV = +2
SOIC
120
80
40
0
-40
OUTPUT VOLTAGE (mV)
-80
-120
-160
TIME (5ns/DIV.)
FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL PULSE RESPONSE
1.6
AV = +2
SOIC
1.2
V
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
SUPPLY
RL = 100Ω, Unless Otherwise Specified
1.6
1.2
0.8
0.4
0
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
160
120
AV = +2
SOIC
TIME (5ns/DIV.)
AV = -1
SOIC
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
0
TIME (5ns/DIV.)
80
40
0
-40
OUTPUT VOLTAGE (mV)
-80
-120
-160
TIME (5ns/DIV.)
FIGURE 6. LARGE SIGNAL PULSE RESPONSE FIGURE 7. SMALL SIGNAL PULSE RESPONSE
1.6
1.2
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
AV = -1
SOIC
0
1.6
1.2
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
AV = -1
SOIC
0
-1.2
-1.6
TIME (5ns/DIV.)
-1.2
-1.6
TIME (5ns/DIV.)
FIGURE 8. LARGE SIGNAL PULSE RESPONSE FIGURE 9. LARGE SIGNAL PULSE RESPONSE
7
Page 8
HFA1405
Typical Performance Curves
V
SUPPLY
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
160
120
80
40
0
-40
-80
OUTPUT VOLTAGE (mV)
-120
-160
AV = +6
SOIC
TIME (5ns/DIV.)
1.6
1.2
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
AV = +6
SOIC
0
TIME (5ns/DIV.)
FIGURE 10. SMALL SIGNAL PULSE RESPONSE FIGURE 11. LARGE SIGNAL PULSE RESPONSE
V
= 200mV
OUT
6
SOIC
3
0
-3
-6
NORMALIZED GAIN (dB)
0.3 1 10 100 800
P-P
GAIN
PHASE
AV = +2
AV = -1
AV = +6
= +6
A
V
A
= -1
V
AV = +2
FREQUENCY (MHz)
2
1
0
-1
-2
0
90
180
270
360
NORMALIZED PHASE (DEGREES)
-3
NORMALIZED GAIN (dB)
AV = +2
V
= 200mV
OUT
SOIC
RF= 1kΩ
= 1.5kΩ
R
F
1 10 100 1000
RF= 500Ω
P-P
FREQUENCY (MHz)
R
R
= 683Ω
F
= 750Ω
F
RF= 1.5kΩ
RF= 500Ω
0
90
180
270
PHASE (DEGREES)
360
FIGURE 12. FREQUENCY RESPONSE FIGURE 13. FREQUENCY RESPONSE vs FEEDBACK RESISTOR
0.3
V
= 200mV
OUT
0.2
SOIC
0.1
0
-0.1
-0.2
-0.3
-0.4
NORMALIZED GAIN (dB)
-0.5
-0.6
-0.7
1 10 100
P-P
AV = -1
AV = +2
AV = +6
FREQUENCY (MHz)
FIGURE 14. GAIN FLATNESS FIGURE 15. GAIN FLATNESS vs FEEDBACK RESISTOR
8
0.2
AV = +2, SOIC
0.1
V
= 200mV
OUT
0
-0.1
-0.2
-0.3
-0.4
-0.5
NORMALIZED GAIN (dB)
-0.6
-0.7
-0.8
1 10 100
P-P
RF= 750Ω
RF= 1kΩ
RF= 1.5kΩ
FREQUENCY (MHz)
RF= 500Ω
RF= 683Ω
Page 9
HFA1405
Typical Performance Curves
V
SUPPLY
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
160
AV = +1
PDIP
120
80
40
0
-40
OUTPUT VOLTAGE (mV)
-80
-120
-160
TIME (5ns/DIV.)
1.6
AV = +1
PDIP
1.2
0.8
0.4
0
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
TIME (5ns/DIV.)
FIGURE 16. SMALL SIGNAL PULSE RESPONSE FIGURE 17. LARGE SIGNAL PULSE RESPONSE
160
120
AV = -1
PDIP
1.6
1.2
AV = -1
PDIP
80
40
0
-40
OUTPUT VOLTAGE (mV)
-80
-120
-160
TIME (5ns/DIV.)
0.8
0.4
0
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
TIME (5ns/DIV.)
FIGURE 18. SMALL SIGNAL PULSE RESPONSE FIGURE 19. LARGE SIGNAL PULSE RESPONSE
160
AV = +2
PDIP
120
80
40
0
-40
OUTPUT VOLTAGE (mV)
-80
1.6
AV = +2
PDIP
1.2
0.8
0.4
0
-0.4
OUTPUT VOLTAGE (V)
-0.8
-120
-160
TIME (5ns/DIV.)
-1.2
-1.6
TIME (5ns/DIV.)
FIGURE 20. SMALL SIGNAL PULSE RESPONSE FIGURE 21. LARGE SIGNAL PULSE RESPONSE
9
Page 10
HFA1405
Typical Performance Curves
V
SUPPLY
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
160
120
80
40
0
-40
OUTPUT VOLTAGE (mV)
-80
-120
-160
AV = +6
AV = +2
PDIP
PDIP
R
= 150Ω
F
TIME (5ns/DIV.)
1.6
AV = +6
PDIP
1.2
RF= 150Ω
0.8
0.4
0
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
TIME (5ns/DIV.)
FIGURE 22. SMALL SIGNAL PULSE RESPONSE FIGURE 23. LARGE SIGNAL PULSE RESPONSE
160
120
AV = +6
PDIP
RF= 500Ω
80
1.6
1.2
0.8
AV = +6
PDIP
R
= 500Ω
F
40
0
-40
OUTPUT VOLTAGE (mV)
-80
-120
-160
TIME (5ns/DIV.)
0.4
0
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
TIME (5ns/DIV.)
FIGURE 24. SMALL SIGNAL PULSE RESPONSE FIGURE 25. LARGE SIGNAL PULSE RESPONSE
V
= 200mV
OUT
PDIP
3
0
-3
-6
NORMALIZED GAIN (dB)
0.3 1 10 100 800
P-P
= +1 (RF = +RS = 510Ω)
A
V
FREQUENCY (MHz)
AV = +2
AV = -1
AV = +2
= -1
A
V
= +1
A
V
0
90
180
270
360
NORMALIZED PHASE (DEGREES)
AV = +6
V
= 200mV
OUT
3
PDIP
0
-3
-6
NORMALIZED GAIN (dB)
0.3
P-P
1 10 100 800
RF = 150Ω
RF = 500Ω
RF = 500Ω
= 150Ω
R
F
FREQUENCY (MHz)
0
90
180
270
360
PHASE (DEGREES)
FIGURE 26. FREQUENCY RESPONSE FIGURE 27. FREQUENCY RESPONSE
10
Page 11
HFA1405
Typical Performance Curves
V
SUPPLY
RL = 100Ω, Unless Otherwise Specified (Continued)
3
V
= 5V
OUT
2
PDIP
1
0
-1
-2
-3
NORMALIZED GAIN (dB)
-4
0.3
P-P
AV = +2
AV = +6 (RF = 500Ω)
AV = +6
(RF = 150Ω)
1 10 100 800
FREQUENCY (MHz)
FIGURE 28. FULL POWER BANDWIDTH FIGURE 29. FREQUENCY RESPONSE vs FEEDBACKRESISTOR
V
= 200mV
OUT
0.2
PDIP
0.1
0
-0.1
-0.2
-0.3
NORMALIZED GAIN (dB)
1 10 100
P-P
AV = +1 (RF = +RS = 510Ω)
AV = +6
(RF = 150Ω)
FREQUENCY (MHz)
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
AV = +2
A
AV = +2
AV = -1
V
= -1
2
1
0
-1
-2
-3
NORMALIZED GAIN (dB)
-42
-43
-44
-45
-46
-47
-48
-49
-50
-51
DISTORTION (dBc)
-52
-53
-54
-55
= 200mV
V
OUT
PDIP
1 10 100 800
-50 -25 0 25 50 75 100 125
P-P
FREQUENCY (MHz)
20MHz
10MHz
TEMPERATURE (oC)
RF = 365Ω
RF = 390Ω
RF = 422Ω
RF = 510Ω
FIGURE 30. GAIN FLATNESS FIGURE 31. 2nd HARMONIC DISTORTION vs TEMPERATURE
-55
-56
-57
-58
-59
-60
-61
-62
-63
DISTORTION (dBc)
-64
-65
-66
-67
-50 -25 0 25 50 75 100 125
20MHz
10MHz
TEMPERATURE (oC)
3.6
AV = -1
3.5
3.4
3.3
3.2
3.1
3.0
2.9
OUTPUT VOLTAGE (V)
2.8
2.7
2.6
-50 -25 0 25 50 75 100 125
|-V
+V
| (RL= 50Ω)
OUT
+V
(RL= 100Ω)
OUT
(RL= 50Ω)
OUT
TEMPERATURE (
|-V
OUT
o
C)
| (RL= 100Ω)
FIGURE 32. 3rd HARMONIC DISTORTION vs TEMPERATURE FIGURE 33. OUTPUT VOLTAGE vs TEMPERATURE
11
Page 12
HFA1405
Typical Performance Curves
V
SUPPLY
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
6.6
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
SUPPLY CURRENT (mA / AMPLIFIER)
5.5
4.5 6.55 5.5 6 7
SUPPLY VOLTAGE (±V)
0.2
0.15
0.1
0.05
0.025
0
-0.025
-0.05
-0.1
SETTLING ERROR (%)
-0.15
-0.2
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 35. SETTLING RESPONSE
-10
SOIC
-20
-30
-40
-50
-60
-70
CROSSTALK (dB)
-80
-90
-100
-110
0.3 1 10 100 200
FREQUENCY (MHz)
RL= 100Ω
R
= ∞
L
PDIP
-10
-20
-30
-40
-50
-60
-70
CROSSTALK (dB)
-80
-90
-100
0.3 1 10 100
FREQUENCY (MHz)
RL= 100Ω
RL= ∞
AV = +2
V
OUT
= 2V
FIGURE 36. ALL HOSTILE CROSSTALK FIGURE 37. ALL HOSTILE CROSSTALK
12
Page 13
Die Characteristics
HFA1405
DIE DIMENSIONS:
79 mils x 118 mils x 19 mils
2000µm x 3000µm x 483µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8k
Å ±0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16k
Å ±0.8kÅ
Metallization Mask Layout
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
PASSIVATION:
Type: Nitride
Thickness: 4k
Å ±0.5kÅ
TRANSISTOR COUNT:
320
HFA1405
OUT1 OUT4-IN1 -IN4
+IN1
V+
+IN2
+IN4
V-
+IN3
-IN3-IN2 OUT3OUT2 V-
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are soldby description only. IntersilCorporation reservesthe right to make changes in circuit design and/orspecificationsat any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. Howe ver, no responsibility isassumedby Intersil or its subsidiaries for its use; nor for any infringements of patents orother rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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