Page 1
HFA1305
Data Sheet April 1999
Triple, 560MHz, Low Power, Video
Operational Amplifier
The HFA1305 is a triple, high speed, low power current
feedback amplifier built with Intersil’s proprietary
complementary bipolar UHF-1 process.
These amplifiers deliver up to 560MHz bandwidth and
1700V/µs slew rate,ononly58mWofquiescentpower.They
are specifically designed to meet the performance, power,
and cost requirements of high volume video applications.
The excellent gain flatness and differential gain/phase
performance make these amplifiers well suited for
component or composite video applications. Video
performance is maintained even when driving a double
terminated cable (R
when driving two double terminated cables (R
= 150Ω), and degrades only slightly
L
=75Ω). RGB
L
applications will benefit from the high slew rates, and high
full power bandwidth.
The HFA1305 is a pin compatible, low power, high
performance upgrade for the popular Intersil HA5013, and
for the AD8073 and CLC5623, in ±5V applications.
Ordering Information
TEMP.
PART NUMBER
HFA1305IB -40 to 85 14 Ld SOIC M14.15
HA5025EVAL High Speed Op Amp DIP Evaluation Board
RANGE (oC) PACKAGE
PKG.
NO.
File Number 4727
Features
• Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA/Op Amp
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ
• Wide -3dB Bandwidth (A
= +2). . . . . . . . . . . . . . 560MHz
V
• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1700V/µs
• Gain Flatness (to 50MHz). . . . . . . . . . . . . . . . . . . . ±0.03dB
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Differential Phase. . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• All Hostile Crosstalk (5MHz). . . . . . . . . . . . . . . . . . -60dB
• Pin Compatible Upgrade to HA5013, AD8073 and
CLC5623 in ±5V Supply Applications
Applications
• Flash A/D Drivers
• Professional Video Processing
• Video Digitizing Boards/Systems
• Computer Video Plug-In Boards
• RGB Preamps
• Medical Imaging
• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications
• High Speed Oscilloscopes and Analyzers
Pinout
HFA1305
(SOIC)
TOP VIEW
NC
1
2
NC
3
NC
4
V+
5
+IN 1
-IN 1
OUT 1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
+
-
6
7
| Copyright © Intersil Corporation 1999
14
OUT 3
13
-IN 3
-
+
12
+IN 3
11
V-
10
+IN 2
+
-
9
-IN 2
8
OUT 2
Page 2
HFA1305
Absolute Maximum Ratings T
Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current (Note 2). . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . 600V
= 25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SUPPLY
30mA Continuous
60mA ≤ 50% Duty Cycle
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Output is short circuitprotected to ground.Briefshort circuits togroundwill not degradereliability, however continuous(100%duty cycle) output
current must not exceed 30mA for maximum reliability.
Electrical Specifications V
PARAMETER TEST CONDITIONS
INPUT CHARACTERISTICS
Input Offset Voltage A 25 - 2 5 mV
Average Input Offset Voltage Drift B Full - 1 10 µV/oC
Input Offset Voltage
Common-Mode Rejection Ratio
Input Offset Voltage
Power Supply Rejection Ratio
Non-Inverting Input Bias Current A 25 - 6 15 µA
Non-Inverting Input Bias Current Drift B Full - 5 60 nA/oC
Non-Inverting Input Bias Current
Power Supply Sensitivity
Non-Inverting Input Resistance ∆VCM = ±1.8V A 25 0.8 1.2 - MΩ
Inverting Input Bias Current A 25 - 2 7.5 µA
Inverting Input Bias Current Drift B Full - 60 200 nA/oC
Inverting Input Bias Current
Common-Mode Sensitivity
= ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified
SUPPLY
(NOTE 4)
TESTLEVEL
A Full - 3 8 mV
∆VCM = ±1.8V A 25 45 48 - dB
∆VCM = ±1.8V A 85 43 46 - dB
∆VCM = ±1.2V A -40 43 46 - dB
∆VPS = ±1.8V A 25 48 52 - dB
∆VPS = ±1.8V A 85 46 48 - dB
∆VPS = ±1.2V A -40 46 48 - dB
A Full - 10 25 µA
∆VPS = ±1.8V A 25 - 0.5 1 µA/V
∆VPS = ±1.8V A 85 - 0.8 3 µA/V
∆VPS = ±1.2V A -40 - 0.8 3 µA/V
∆VCM = ±1.8V A 85 0.5 0.8 - MΩ
∆VCM = ±1.2V A -40 0.5 0.8 - MΩ
A Full - 5 15 µA
∆VCM = ±1.8V A 25 - 3 6 µA/V
∆VCM = ±1.8V A 85 - 4 8 µA/V
∆VCM = ±1.2V A -40 - 4 8 µA/V
TEMP.
(oC)
HFA1305IB (SOIC)
UNITSMIN TYP MAX
2
Page 3
HFA1305
Electrical Specifications V
PARAMETER TEST CONDITIONS
Inverting Input Bias Current Power Supply
Sensitivity
Inverting Input Resistance C 25 - 60 - Ω
Input Capacitance B 25 - 1.4 - pF
Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN, and -I
CMS Tests)
Input Noise Voltage Density f = 100kHz B 25 - 3.5 - nV/√Hz
Non-Inverting Input Noise Current Density f = 100kHz B 25 - 2.5 - pA/√Hz
Inverting Input Noise Current Density f = 100kHz B 25 - 20 - pA/√Hz
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain C 25 - 500 - kΩ
AC CHARACTERISTICS (Note 3)
-3dB Bandwidth
(V
= 0.2V
OUT
Full Power Bandwidth
(V
= 5V
OUT
Gain Flatness
(V
= 0.2V
OUT
Minimum Stable Gain A Full - 1 - V/V
Crosstalk
(AV = +2, All Channels Hostile, Note 5)
OUTPUT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified
Output Voltage Swing
(Note 5)
Output Current
(Note 5)
Output Short Circuit Current B 25 - 90 - mA
Closed Loop Output Impedance B 25 - 0.2 - Ω
, Notes 3, 5)
P-P
, Notes 3, 5)
P-P
, Notes 3, 5)
P-P
= ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
HFA1305IB (SOIC)
BIAS
(NOTE 4)
TESTLEVEL
∆VPS = ±1.8V A 25 - 2 5 µA/V
∆VPS = ±1.8V A 85 - 4 8 µA/V
∆VPS = ±1.2V A -40 - 4 8 µA/V
A 25, 85 ±1.8 ±2.4 - V
A -40 ±1.2 ±1.7 - V
AV = +1 B 25 - 375 - MHz
AV = -1 B 25 - 420 - MHz
AV = +2 B 25 - 560 - MHz
AV = +1 B 25 - 160 - MHz
AV = -1 B 25 - 260 - MHz
AV = +2 B 25 - 165 - MHz
AV = +1, To 25MHz B 25 - ±0.03 - dB
AV = +1, To 50MHz B 25 - ±0.03 - dB
AV = +1, To 100MHz B 25 - ±0.07 - dB
AV = -1, To 25MHz B 25 - ±0.03 - dB
AV = -1, To 50MHz B 25 - ±0.04 - dB
AV = +2, To 25MHz B 25 - ±0.03 - dB
AV = +2, To 50MHz B 25 - ±0.03 - dB
AV = +2, To 100MHz B 25 - ±0.07 - dB
5MHz B 25 - -60 - dB
10MHz B 25 - -56 - dB
AV = -1, RL = 100Ω A25±3 ±3.4 - V
A Full ±2.8 ±3- V
AV = -1, RL = 50Ω A 25, 85 50 60 - mA
A -40 28 42 - mA
TEMP.
(oC)
UNITSMIN TYP MAX
3
Page 4
HFA1305
Electrical Specifications V
PARAMETER TEST CONDITIONS
Second Harmonic Distortion
(V
= 2V
OUT
Third Harmonic Distortion
(V
= 2V
OUT
P-P
P-P
, Note 5)
, Note 5)
= ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
(NOTE 4)
TESTLEVEL
TEMP.
(oC)
HFA1305IB (SOIC)
10MHz B 25 - -51 - dBc
20MHz B 25 - -46 - dBc
10MHz B 25 - -63 - dBc
20MHz B 25 - -56 - dBc
UNITSMIN TYP MAX
TRANSIENT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified
Rise and Fall Times
(V
OUT
= 0.5V
P-P
, Note 3)
Overshoot
(V
OUT
= 0.5V
P-P
, VIN t
Notes 3, 6)
RISE
= 1ns,
AV = +1 B 25 - 1.0 - ns
AV = +2 B 25 - 0.8 - ns
AV = +1, +OS B 25 - 5 - %
AV = +1, -OS B 25 - 11 - %
AV = -1, +OS B 25 - 7 - %
AV = -1, -OS B 25 - 8 - %
AV = +2, +OS B 25 - 5 - %
AV = +2, -OS B 25 - 10 - %
Slew Rate
(V
= 5V
OUT
V
= 4V
OUT
Notes 3, 5)
at AV = +2, -1,
P-P
, at AV = +1,
P-P
AV = +1, +SR B 25 - 1230 - V/µs
AV = +1, -SR B 25 - 1350 - V/µs
AV = -1, +SR B 25 - 2500 - V/µs
AV = -1, -SR B 25 - 1900 - V/µs
AV = +2, +SR B 25 - 1700 - V/µs
AV = +2, -SR B 25 - 1700 - V/µs
Settling Time
(V
= +2V to 0V Step, Note 5)
OUT
To 0.1% B 25 - 23 - ns
To 0.05% B 25 - 30 - ns
To 0.025% B 25 - 37 - ns
Overdrive Recovery Time VIN = ±2V B 25 - 8.5 - ns
VIDEO CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified
Differential Gain
(f = 3.58MHz)
Differential Phase
(f = 3.58MHz)
RL = 150Ω B 25 - 0.02 - %
RL = 75Ω B 25 - 0.03 - %
RL = 150Ω B 25 - 0.03 - Degrees
RL = 75Ω B 25 - 0.06 - Degrees
POWER SUPPLY CHARACTERISTICS
Power Supply Range C 25 ±4.5 - ±5.5 V
Power Supply Current (Note 5) A 25 - 5.8 6.1 mA/Op
Amp
A Full - 5.9 6.3 mA/Op
Amp
NOTES:
3. The optimum feedbackresistor dependsonclosed loopgainand packagetype. The followingresistors wereusedfor theSOIC characterization:
AV = -1, RF = 360Ω; AV = +2, RF = 510Ω; AV = +1, RF = 464Ω, +RS = 649Ω. See the Application Information section for more information.
4. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
5. See Typical Performance Curves for more information.
6. Undershoot dominates for output signal swings below GND (e.g., 2V
), yielding a higher overshoot limit compared to the V
P-P
OUT
=0Vto2V
condition. See the “Application Information” section for details.
4
Page 5
HFA1305
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and R
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and R
, in conjunction with
F
the internal compensation capacitor, sets the dominant pole
of the frequency response.Thus,theamplifier’s bandwidth is
inversely proportional to R
optimized for R
R
decreases stability, resulting in excessive peaking and
F
= 510Ω (SOIC) at a gain of +2. Decreasing
F
. The HFA1305 design is
F
overshoot (Note: Capacitive feedback causes the same
problemsduetothefeedbackimpedancedecreaseathigher
frequencies). However, at higher gains the amplifier is more
stable so R
can be decreased in a trade-off of stability for
F
bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth. For good
channel-to-channel gain matching, it is recommended that
all resistors (termination as well as gain setting) be ±1%
tolerance or better.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL)
-1 360 420
+1 464 (+RS = 649) 375
+2 510 560
+5 200 330
+10 180 140
RF (Ω)
SOIC
BANDWIDTH (MHz)
SOIC
Non-Inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be ≥ 50Ω. This is especially
important in inverting gain configurations where the
non-inverting input would normally be connected directly to
GND.
Pulse Undershoot
The HFA1305 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
composite device switches modes after crossing 0V,
resulting in added distortion for signals swinging below
ground, and an increased undershoot on the negative
portion of the output waveform (see Figure 6 and Figure 9).
This undershoot isn’t present for small bipolar signals, or
large positive signals (see Figures4, 7, 10 and Figures 5, 8).
.
F
PC Board Layout
The frequency response of thisamplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance, parasitic or
planned, connected to the output must be minimized, or
isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance,theworsethegain peaking, resulting
in pulse overshoot and eventual instability. To reduce this
capacitance the designer should remove the ground plane
under traces connected to -IN, and keep connections to -IN
as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdampedresponse,whilepointsbelow or left of the curve
indicate areas of underdamped performance.
R
and CLform a low pass network at the output, thus
S
limiting system bandwidth well below the amplifier bandwidth
of 560MHz. By decreasing R
in the curve), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth still decreases
as the load capacitance increases.
) in series with the output
S
and C
S
as CLincreases (as illustrated
S
L
5
Page 6
HFA1305
50
40
30
20
A
= +2
10
SERIES OUTPUT RESISTANCE (Ω)
0
0 100 200 300 400
V
150 250 35050
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTORvs
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1305IB (SOIC) may be
evaluated using the HA5025 Evaluation Board and a SOIC
to DIP adaptor like the Aries 14-350000-10 part.
The schematic for amplifier 1 and the board layout are
shown in Figure 2 and Figure 3. Resistors R
may require a change to values applicable to the HFA1305.
, RG and R
F
S
TOP LAYOUT
BOTTOM LAYOUT
To order evaluation boards (part number HA5025EVAL),
please contact your local sales office.
1
10µF 0.1µF
+5V
50Ω
IN
R
OUT
50Ω
G
R
S
2
3
4
5
+
-
6
R
F
7
FIGURE 2. EVALUATION BOARD SCHEMATIC
14
13
12
11
10
0.1µF
9
8
GND
10µF
GND
FIGURE 3. EVALUATION BOARD LAYOUT
-5V
6
Page 7
HFA1305
Typical Performance Curves V
160
AV = +2
SOIC
120
80
40
0
-40
-80
OUTPUT VOLTAGE (mV)
-120
-160
TIME (5ns/DIV.)
FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL PULSE RESPONSE
1.6
AV = +2
SOIC
1.2
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL =
SUPPLY
100Ω, Unless Otherwise Specified
1.6
1.2
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
160
120
AV = +2
SOIC
0
TIME (5ns/DIV.)
AV = -1
SOIC
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
0
TIME (5ns/DIV.)
80
40
0
-40
-80
OUTPUT VOLTAGE (mV)
-120
-160
TIME (5ns/DIV.)
FIGURE 6. LARGE SIGNAL PULSE RESPONSE FIGURE 7. SMALL SIGNAL PULSE RESPONSE
1.6
1.2
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
AV = -1
SOIC
0
1.6
1.2
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
AV = -1
SOIC
0
-1.2
-1.6
TIME (5ns/DIV.)
-1.2
-1.6
TIME (5ns/DIV.)
FIGURE 8. LARGE SIGNAL PULSE RESPONSE FIGURE 9. LARGE SIGNAL PULSE RESPONSE
7
Page 8
HFA1305
Typical Performance Curves V
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL =
SUPPLY
100Ω, Unless Otherwise Specified (Continued)
160
120
80
40
0
-40
-80
OUTPUT VOLTAGE (mV)
-120
-160
AV = +1
SOIC
TIME (5ns/DIV.)
1.6
1.2
0.8
0.4
-0.4
OUTPUT VOLTAGE (V)
-0.8
-1.2
-1.6
AV = +1
SOIC
0
TIME (5ns/DIV.)
FIGURE 10. SMALL SIGNAL PULSE RESPONSE FIGURE 11. LARGE SIGNAL PULSE RESPONSE
V
= 200mV
OUT
6
SOIC
3
0
-3
-6
NORMALIZED GAIN (dB)
0.3 1 10 100 800
P-P
GAIN
PHASE
AV = +2
AV = -1
= +1
A
V
A
= -1
V
AV = +2
FREQUENCY (MHz)
AV = +1
2
1
0
-1
-2
0
90
180
270
360
NORMALIZED PHASE (DEGREES)
-3
NORMALIZED GAIN (dB)
AV = +2
V
= 200mV
OUT
SOIC
RF= 1kΩ
= 1.5kΩ
R
F
1 10 100 1000
RF= 500Ω
P-P
FREQUENCY (MHz)
R
R
= 683Ω
F
= 750Ω
F
RF= 1.5kΩ
RF= 500Ω
0
90
180
270
PHASE (DEGREES)
360
FIGURE 12. FREQUENCY RESPONSE FIGURE 13. FREQUENCY RESPONSE vs FEEDBACK RESISTOR
0.3
V
= 200mV
OUT
0.2
SOIC
0.1
0
-0.1
-0.2
-0.3
-0.4
NORMALIZED GAIN (dB)
-0.5
-0.6
-0.7
1 10 100
P-P
AV = +1
FREQUENCY (MHz)
FIGURE 14. GAIN FLATNESS FIGURE 15. GAIN FLATNESS vs FEEDBACK RESISTOR
8
AV = -1
AV = +2
AV = +2
0.2
AV = +2, SOIC
0.1
V
= 200mV
OUT
0
-0.1
-0.2
-0.3
-0.4
-0.5
NORMALIZED GAIN (dB)
-0.6
-0.7
-0.8
1 10 100
P-P
RF= 750Ω
RF= 1kΩ
RF= 1.5kΩ
FREQUENCY (MHz)
RF= 500Ω
RF= 683Ω
Page 9
HFA1305
Typical Performance Curves V
= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL =
SUPPLY
100Ω, Unless Otherwise Specified (Continued)
-42
-43
-44
-45
-46
-47
-48
-49
-50
-51
DISTORTION (dBc)
-52
-53
-54
-55
-50 -25 0 25 50 75 100 125
20MHz
10MHz
TEMPERATURE (oC)
-55
-56
-57
-58
-59
-60
-61
-62
-63
DISTORTION (dBc)
-64
-65
-66
-67
-50 -25 0 25 50 75 100 125
20MHz
10MHz
TEMPERATURE (oC)
FIGURE 16. 2nd HARMONIC DISTORTION vs TEMPERATURE FIGURE 17. 3rd HARMONIC DISTORTION vs TEMPERATURE
3.6
AV = -1
3.5
3.4
3.3
3.2
3.1
3.0
2.9
OUTPUT VOLTAGE (V)
2.8
2.7
2.6
-50 -25 0 25 50 75 100 125
|-V
+V
| (RL= 50Ω)
OUT
+V
(RL= 100Ω)
OUT
(RL= 50Ω)
OUT
TEMPERATURE (
|-V
o
C)
| (RL= 100Ω)
OUT
6.6
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
SUPPLY CURRENT (mA / AMPLIFIER)
5.5
4.5 6.55 5.5 6 7
SUPPLY VOLTAGE (V)
FIGURE 18. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 19. SUPPLY CURRENT vs SUPPLY VOLTAGE
-10
SOIC
-20
-30
-40
-50
-60
-70
CROSSTALK (dB)
-80
-90
-100
-110
0.3 1 10 100 200
FREQUENCY (MHz)
RL= 100Ω
R
= ∞
L
FIGURE 21. ALL HOSTILE CROSSTALK
0.2
0.15
0.1
0.05
0.025
0
-0.025
-0.05
-0.1
SETTLING ERROR (%)
-0.15
-0.2
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
FIGURE 20. SETTLING RESPONSE
AV = +2
V
OUT
= 2V
Die Characteristics
9
Page 10
HFA1305
DIE DIMENSIONS:
79 mils x 118 mils x 19 mils
2000µm x 3000µm x 483µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8k
Å ±0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16k
Å ±0.8kÅ
Metallization Mask Layout
NC
SUBSTRATE POTENTIAL (POWERED UP):
Floating (Recommend Connection to V-)
PASSIVATION:
Type: Nitride
Thickness: 4k
Å ±0.5kÅ
TRANSISTOR COUNT:
240
HFA1305
NC OUT3NC -IN3
+IN3
V+
+IN1
V-
+IN2
-IN2-IN1 OUT2OUT1 V-
10
Page 11
Small Outline Plastic Packages (SOIC)
HFA1305
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010) BM M
H
L
h x 45
o
α
e
B
0.25(0.010) C AM BS
M
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” doesnotinclude interlead flashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
A1
C
0.10(0.004)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC H 0.2284 0.2440 5.80 6.20 h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N14 147
o
α
0
o
8
o
0
o
8
Rev. 0 12/93
NOTESMIN MAX MIN MAX
-
11
Page 12
HFA1305
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12
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