Datasheet HFA1212 Datasheet (Intersil Corporation)

HFA1212

September 1998 File Number 3607.4

Dual 350MHz, Low Power Closed Loop
Buffer Amplifier

The HFA1212 is a dual closed loop Buffer featuring user
programmable gain and high speed performance.
Manufactured on Intersil’s proprietary complementary
bipolar UHF-1 process, these devices offer wide -3dB
bandwidth of 350MHz, very fast slew rate, excellent gain
flatness and high output current.

A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via
connections to the inputs, as described in the “Application
Information” section. The result is a more flexible product,
fewerpart types in inventory, and more efficient use of board
space.

Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date. For Military product, refer to the HFA1212/883
data sheet.

Ordering Information

PART NUMBER

(BRAND)

HFA1212IP -40 to 85 8 Ld PDIP E8.3
HFA1212IB

(H1212I)

TEMP.

RANGE (oC) PACKAGE

-40 to 85 8 Ld SOIC M8.15

PKG.

NO.

Features

• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025%

• Differential Phase. . . . . . . . . . . . . . . . . . . . 0.03 Degrees

• Wide -3dB Bandwidth (A

• Very Fast Slew Rate (A

= +2). . . . . . . . . . . . . .350MHz

V

= -1) . . . . . . . . . . . . . . 1100V/µs

V

• Low Supply Current . . . . . . . . . . . . . . . . . . . . 6mA/Buffer

• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . .60mA

• Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V

• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors

• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns

• Standard Operational Amplifier Pinout

Applications

• High Resolution Monitors

• Professional Video Processing

• Medical Imaging

• Video Digitizing Boards/Systems

• RF/IF Processors

• Battery Powered Communications

• Flash Converter Drivers

• High Speed Pulse Amplifiers

Pinout

HFA1212

(PDIP, SOIC)

TOP VIEW

OUT1

1
2

-IN1
3

+IN1

4

V-

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

-

+

8

V+

+

7

OUT2

6

-IN2

­5

+IN2

HFA1212

Absolute Maximum Rating Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Output Current (Note 1). . . . . . . . . . . . . . . . .Short Circuit Protected

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . . .600V

SUPPLY

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 30mA for maximum reliability.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications V

PARAMETER

INPUT CHARACTERISTICS

Output Offset Voltage A 25 - 2 10 mV

Average Output Offset Voltage Drift B Full - 22 70 µV/oC
Channel-to-Channel Output Offset

Voltage Mismatch

Common-Mode Rejection Ratio ∆VCM = ±1.8V A 25 42 45 - dB

Power Supply Rejection Ratio ∆VPS = ±1.8V A 25 45 49 - dB

Input Bias Current A 25 - 1 15 µA

Input Bias Current Drift B Full - 30 80 nA/oC
Channel-to-Channel Input Bias Current

Mismatch

Input Bias Current Power Supply Sensitivity ∆VPS = ±1.25V A 25 - 0.5 1 µA/V

Input Resistance ∆VCM = ±1.8V A 25 0.8 1.1 - MΩ

Inverting Input Resistance C 25 - 350 - Ω
Input Capacitance C 25 - 2 - pF
Input Voltage Common Mode Range

(Implied by VIO CMRR and +RIN tests)

Input Noise Voltage Density (Note 4) f = 100kHz B 25 - 7 - nV/√Hz
Input Noise Current Density (Note 4) f = 100kHz B 25 - 3.6 - pA/√Hz

= ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified.

SUPPLY

(NOTE 3)

TEST

CONDITIONS

∆VCM = ±1.8V A 85 40 44 - dB
∆VCM = ±1.2V A -40 40 45 - dB

∆VPS = ±1.8V A 85 43 48 - dB
∆VPS = ±1.2V A -40 43 48 - dB

∆VCM = ±1.8V A 85 0.5 1.4 - MΩ
∆VCM = ±1.2V A -40 0.5 1.3 - MΩ

TEST

LEVEL

A Full - 3 15 mV

A 25 - - 15 mV
A Full - - 30 mV

A Full - 3 25 µA

A 25 - - 15 µA
A Full - - 25 µA

A Full - - 3 µA/V

A 25, 85 ±1.8 ±2.4 - V
A -40 ±1.2 ±1.7 - V

TEMP

(oC) MIN TYP MAX UNITS

2

HFA1212

Electrical Specifications V

= ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued)

SUPPLY

(NOTE 3)

PARAMETER

TEST

CONDITIONS

TEST

LEVEL

TEMP

(oC) MIN TYP MAX UNITS

TRANSFER CHARACTERISTICS

Gain (VIN = -1V to +1V) AV = -1 A 25 -0.98 0.996 -1.02 V/V

A Full 0.975 1.000 -1.025 V/V

AV = +1 A 25 0.98 0.992 1.02 V/V

A Full 0.975 0.993 1.025 V/V

AV = +2 A 25 1.96 1.988 2.04 V/V

A Full 1.95 1.990 2.05 V/V

Channel-to-Channel Gain Mismatch AV = -1 A 25 - - ±0.02 V/V

A Full - - ±0.025 V/V

AV = +1 A 25 - - ±0.025 V/V

A Full - - ±0.025 V/V

AV = +2 A 25 - - ±0.04 V/V

A Full - - ±0.05 V/V

AC CHARACTERISTICS

-3dB Bandwidth
(V

= 0.2V

OUT

P-P

, Note 4)

AV = -1 B 25 - 300 - MHz
AV= +1, +RS= 620Ω B 25 - 240 - MHz
AV = +2 B 25 - 350 - MHz

Full Power Bandwidth
(V
V

OUT

OUT

= 5V

= 4V

at AV = +2 or -1,

P-P

at AV = +1, Note 4)

P-P

AV = -1 B 25 - 165 - MHz
AV = +1, +RS= 620Ω B 25 - 150 - MHz
AV = +2 B 25 - 125 - MHz

Gain Flatness
(V

OUT

= 0.2V

P-P

, Note 4)

Crosstalk
(All Channels Hostile, Note 4)

AV = +2, To 25MHz B 25 - ±0.03 - dB
AV = +2, To 50MHz B 25 - ±0.04 - dB
5MHz B 25 - -65 - dB
10MHz B 25 - -60 - dB

OUTPUT CHARACTERISTICS

Output Voltage Swing
(Note 4)

Output Current
(Note 4)

AV = -1 A 25 ±3.0 ±3.2 - V

A Full ±2.8 ±3.0 - V

AV = -1, RL = 50Ω A 25, 85 50 55 - mA

A -40 28 42 - mA
Output Short Circuit Current B 25 - 100 - mA
DC Closed Loop Output Impedance AV= +2 B 25 - 0.2 - Ω
Second Harmonic Distortion

(AV= +2, V

OUT

=2V

P-P

, Note 4)

Third Harmonic Distortion
(AV= +2, V

OUT

=2V

P-P

, Note 4)

10MHz B 25 - -60 - dBc
20MHz B 25 - -50 - dBc
10MHz B 25 - -60 - dBc

20MHz B 25 - -50 - dBc
Reverse Isolation (S12, Note 4) 30MHz, AV= +2 B 25 - -65 - dB
TRANSIENT RESPONSE AV= +2, Unless Otherwise Specified
Rise and Fall Times

(V

OUT

= 0.5V

P-P

)

Rise Time B 25 - 1.0 - ns

Fall Time B 25 - 1.1 - ns

3

HFA1212

Electrical Specifications V

PARAMETER

Overshoot
(V

= 0.5V

OUT

Slew Rate
(V

= 5V

OUT

V

= 4V

OUT

Settling Time
(V

= +2V to 0V Step, Note 4)

OUT

Overdrive Recovery Time VIN= ±2V B 25 - 8.5 - ns

VIDEO CHARACTERISTICS

Differential Gain (f = 3.58MHz, AV = +2) RL = 150Ω B 25 - 0.025 - %
Differential Phase (f = 3.58MHz, AV = +2) RL = 150Ω B 25 - 0.03 - Degrees

POWER SUPPLY CHARACTERISTICS

Power Supply Range C 25 ±4.5 - ±5.5 V
Power Supply Current A 25 - 5.9 6.1 mA/Op Amp

NOTES:

3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.

4. See Typical Performance Curves for more information.

5. Negative overshoot dominates for output signal swings below GND (e.g. 0.5V
V

OUT

, VIN t

P-P

at AV = +2 or -1,

P-P

at AV = +1)

P-P

= 0V to 0.5V condition. See the “Application Information” section for details.

= 1ns, Note 5)

RISE

= ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued)

SUPPLY

(NOTE 3)

TEST

CONDITIONS

+OS B 25 - 4 - %

-OS B 25 - 13 - %
AV= -1 +SR B 25 - 2000 - V/µs

-SR B 25 - 1150 - V/µs

AV= +1,
+RS = 620Ω

AV= +2 +SR B 25 - 1300 - V/µs

To 0.1% B 25 - 24 - ns
To 0.05% B 25 - 37 - ns
To 0.02% B 25 - 60 - ns

+SR B 25 - 1100 - V/µs

-SR B 25 - 850 - V/µs

-SR B 25 - 900 - V/µs

TEST

LEVEL

P-P

TEMP

(oC) MIN TYP MAX UNITS

A Full - 6.1 6.3 mA/Op Amp

), yielding a higher overshoot limit compared to the

Application Information

HFA1212 Advantages

The HFA1212 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexibleproduct, fewer part
types in inventory, and more efficient use of board space.
Implementing a dual, gain of 2, cable driver with this IC
eliminates the four gain setting resistors, which frees up
board space for termination resistors.

Likemost newer high performance amplifiers,the HFA1212is a
current feedback amplifier (CFA). CFAs offer high bandwidth
and slew rate at low supply currents, b ut can be difficult to use
because of their sensitivity to feedback capacitance and
parasiticson the invertinginput (summing node). The HFA1212
eliminates these concerns by bringing the gain setting resistors
on-chip. This yields the optimum placement and value of the
feedback resistor, while minimizing feedback and summing
node parasitics. Because there is no access to the summing
node,the PCB parasiticsdo not impactperformance at gains of

4

+2 or -1 (see “Unity Gain Considerations” for discussion of
parasitic impact on unity gain performance).

The HFA1212’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.

Closed Loop Gain Selection

This “buffer” operates in closed loop gains of -1, +1, or +2, with
gain selection accomplished via connections to the inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for la y out ca v eats), while g rounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded through a 50Ω resistor.

The table below summarizes these connections:

GAIN
(ACL)

-1 50Ω to GND Input

+1 Input NC (Floating)
+2 Input GND

+INPUT -INPUT

CONNECTIONS

HFA1212

Unity Gain Considerations

Unity gain selection is accomplished by floating the -Input of
the HFA1212.Anything that tendsto short the -Input to GND,
such as stray capacitance at high frequencies, will cause the
amplifier gain to increase toward a gain of +2. The result is
excessive high frequency peaking, and possible instability.
Even the minimal amount of capacitance associated with
attaching the -Input lead to the PCB results in approximately
6dB of gain peaking. At a minimum this requires due care to
ensure the minimum capacitance at the -Input connection.

Table 1 lists five alternatemethods for configuring the HFA1212
as a unity gain buffer, and the corresponding performance. The
implementations vary in complexity and involv e performance
trade-offs. The easiest approach to implement is simply
shorting the two input pins together, and applying the input
signal to this common node. The amplifier bandwidth
decreases from 430MHz to 280MHz,but excellentgain flatness
is the benefit. A drawback to this approach is that the amplifier
input noise voltage and input offset voltageterms see a gain of
+2, resulting in higher noise and output offset voltages.
Alternately , a 100pF capacitor between the inputs shorts them
only at high frequencies, which prevents the increased output
offset voltage but delivers less gain flatness .

Another straightforward approach is to add a 620Ω resistor
in series with the amplifier’s positive input. This resistor and
the HFA1212 input capacitance form a low pass filter which
rolls off the signal bandwidth before gain peaking occurs.
This configuration wasemployedto obtain the data sheet AC
and transient parameters for a gain of +1.

Pulse Overshoot

The HF A1212 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor . The composite de vice
switches modes after crossing 0V, resulting in added distortion
for signals swingingbelow ground, and an increased overshoot
on the negative portion of the output waveform (see Figure 6,
Figure 9, and Figure 12). This overshoot isn’t present for small
bipolar signals (see Figure 4, Figure 7, and Figure 10) or large
positive signals (see Figure 5, Figure 8 and Figure 11).

PC Board Layout

This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB). The use of low

inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!

Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.

Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.

An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.

Driving Capacitive Loads

Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
prior to the capacitance.

Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdampedresponse, while pointsbelow or left of the curve
indicate areas of underdamped performance.

R

and CL form a low pass network at the output, thus

S

limiting system bandwidth well below the amplifierbandwidth
of 350MHz. By decreasing R
illustrated in the curves), the maximum bandwidth is
obtained without sacrificing stability. In spite of this,
bandwidth decreases as the load capacitance increases.

TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS

IMPLEMENTATIONS

PEAKING

APPROACH

Remove -IN Pin 4.5 430 21
+RS= 620Ω 0 220 27
+RS= 620Ω and

Remove -IN Pin
Short +IN to -IN (e.g.,

Pins 2 and 3)
100pF Capacitor

Between +IN and -IN

50

40

30

20

10

SERIES OUTPUT RESISTANCE (Ω)

0

0 100 200 300 400

FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD

CAPACITANCE

(dB)

AV=+2

150 250 35050

LOAD CAPACITANCE (pF)

) in series with the output

S

and C

S

as CL increases (as

S

BW

(MHz)

0.5 215 15

0.6 280 70

0.7 290 40

AV=+1

±0.1dB GAIN

FLATNESS (MHz)

L

5

Evaluation Board

The performance of the HFA1212 may be evaluated using
the HA5023 Evaluation Board, slightly modified as follows:

1. Remove the two feedback resistors, and leave the con­nections open.

2. a. ForA
b. For A

3. Replace the 0Ω series output resistors with 50Ω.

The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.

= +1 evaluation, remove the gain setting

V

resistors (R

V

), and leave pins 2 and 6 floating.

1

= +2, replacethe gain setting resistors (R1) with

0Ω resistors to GND.

HFA1212

To order evaluation boards (part number HA5023EVAL),
please contact your local sales office.

50Ω

OUT

R

(NOTE)

1

IN

50Ω

−5V
10µF 0.1µF

FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC

Typical Performance Curves

200

A

= +2

V

150

1
2
3
4

−
+

8
7
6
5

GND

NOTE: R1=

or 0Ω (A

V

0.1µF

SUPPLY

10µF

GND

∞ (A

=+1)

V

=+2)

V

= ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified

+5V

FIGURE 3A. TOP LAYOUT

FIGURE 3B. BOTTOM LAYOUT

FIGURE 3. EVALUATION BOARD LAYOUT

2.0
A

= +2

V

1.5

100

50

0

-50

OUTPUT VOLTAGE (mV)

-100

-150

-200
TIME (5ns/DIV.)

1.0

0.5

0

-0.5

-1.0

OUTPUT VOLTAGE (V)

-1.5

-2.0
TIME (5ns/DIV.)

FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE

6

HFA1212

Typical Performance Curves

2.0
A

= +2

V

1.5

1.0

0.5

0

-0.5

-1.0

OUTPUT VOLTAGE (V)

-1.5

-2.0
TIME (5ns/DIV.)

(Continued) V

= ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified

SUPPLY

200

150

100

-100

OUTPUT VOLTAGE (mV)

-150

-200

-50

= +1

A

V

50

0

TIME (5ns/DIV.)

FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 7. SMALL SIGNAL PULSE RESPONSE

2.0

1.5

1.0

A

= +1

V

2.0

1.5

1.0

A

= +1

V

0.5

-0.5

-1.0

OUTPUT VOLTAGE (V)

-1.5

-2.0

0

TIME (5ns/DIV.)

0.5

-0.5

OUTPUT VOLTAGE (V)

-1.0

-1.5

-2.0

0

TIME (5ns/DIV.)

FIGURE 8. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE

200

150

100

50

0

-50

-100

OUTPUT VOLTAGE (mV)

-150

= -1

A

V

2.0

1.5

1.0

0.5

-0.5

-1.0

OUTPUT VOLTAGE (V)

-1.5

A

= −1

V

0

-200
TIME (5ns/DIV.)

-2.0
TIME (5ns/DIV.)

FIGURE 10. SMALL SIGNAL PULSE RESPONSE FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE

7

HFA1212

Typical Performance Curves

2.0
= -1

A

V

1.5

1.0

0.5

0

-0.5

-1.0

OUTPUT VOLTAGE (V)

-1.5

-2.0
TIME (5ns/DIV.)

(Continued) V

= ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified

SUPPLY

6
3
0

-3

-6

-9

NORMALIZED GAIN (dB)

GAIN

PHASE

V

= 200mV

OUT

+RS = 620Ω (+1)
+R

= 0Ω (-1, +2)

S

1 10 100 600

P-P

FREQUENCY (MHz)

AV = +1

AV = -1

AV = +1

AV = +2

FIGURE 12. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 13. FREQUENCY RESPONSE

6
3
0

-3

-6

-9

NORMALIZED GAIN (dB)

V

= 4V
= 5V

(+1)

P-P

(-1, +2)

P-P

FREQUENCY (MHz)

OUT

V

OUT

+R

= 620Ω (+1)

S

1 10 100 300

AV = -1
A

= +2

V

A

= +1

V

0.7
V

= 200mV

OUT

0.6

+RS = 620Ω (+1)

= 0Ω (-1, +2)

+R

0.5

S

0.4

0.3

0.2

0.1

0

NORMALIZED GAIN (dB)

-0.1

-0.2

-0.3
1 10 100

P-P

AV = +2

AV = +1

FREQUENCY (MHz)

AV = +2

0

-90

-180

-270

-360
NORMALIZED PHASE (DEGREES)

AV = -1

FIGURE 14. FULL POWER BANDWIDTH FIGURE 15. GAIN FLATNESS

-10

-20

-30

-40

-50

-60

GAIN (dB)

-70

-80

-90

-100

-110

0.3 1 10 100
FREQUENCY (MHz)

AV = -1

AV = +1

AV = +2

FIGURE 16. REVERSE ISOLATION FIGURE 17. ALL HOSTILE CROSSTALK

8

-10
AV = +2

-20

-30

-40

-50

-60

-70

CROSSTALK (dB)

-80

-90

-100

-110

0.3 1 10 100 500
FREQUENCY (MHz)

RL = ∞

RL = 100Ω

HFA1212

Typical Performance Curves

-40

-45

-50

-55

-60

DISTORTION (dBc)

-65

-70

-10 -5 0 5 10

FIGURE 18. 2nd HARMONIC DISTORTION vs P

0.10

0.05

AV = +1

20MHz

10MHz

OUTPUT POWER (dBm)

(Continued) V

OUT

= ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified

SUPPLY

-40

-45

-50

-55

DISTORTION (dBc)

-60

-65

15

-70

-10 -5 0 5 10 15

20MHz

10MHz

OUTPUT POWER (dBm)

FIGURE 19. 3rd HARMONIC DISTORTION vs P

20

16

OUT

20

16

-0.05

SETTLING ERROR (%)

-0.10

0

13 33 53 73 93 113 153 173133

TIME (ns)

12

8

NOISE VOLTAGE (nV/√Hz)

4

0

0.1 1 10 100
FREQUENCY (kHz)

FIGURE 20. SETTLING RESPONSE FIGURE 21. INPUT NOISE CHARACTERISTICS

3.6
A

= -1

V

3.5

3.4

3.3

3.2

3.1

3.0

2.9

OUTPUT VOLTAGE (V)

2.8

2.7

2.6

-50 -25 0 25 50 75 100 125

|-V

| (RL= 50Ω)

OUT

+V

+V

OUT

OUT

(RL= 50Ω)

|-V

OUT

(RL= 100Ω)

TEMPERATURE (

| (RL= 100Ω)

o

C)

12

E

NI

I

NI

8

NOISE CURRENT (pA/√Hz)

4

0

FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE

9

Die Characteristics

HFA1212

DIE DIMENSIONS:

69 mils x 92 mils x 19 mils
1750µm x 2330µm x 483µm

METALLIZATION:

Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8k

Å ±0.4kÅ

Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16k

Å ±0.8kÅ

Metallization Mask Layout

NC

-IN1

HFA1212

OUT1

PASSIVATION:

Type: Nitride
Thickness: 4k

Å ±0.5kÅ

TRANSISTOR COUNT:

180

SUBSTRATE POTENTIAL (Powered Up):

Floating (Recommend Connection to V-)

NC

V+

+IN1

NC

NC

V-

NC

+IN2

OUT2

-IN2

NC

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

10