Datasheet HFA1145 Datasheet (Intersil Corporation)

Page 1
HFA1145
Data Sheet September 1998 File Number 3955.3
330MHz, Low Power, Current Feedback Video Operational Amplifier with Output Disable
This amplifier features a TTL/CMOS compatible disable control, pin 8, which when pulled low reduces the supply current and forces the output into a high impedance state. This allows easy implementation of simple, low power video switching and routing systems. Component and composite video systems also benefit from this op amp’s excellent gain flatness, and good differential gain and phase specifications.
Multiplexed A/D applications will also find the HFA1145 useful as the A/D driver/multiplexer.
The HFA1145 is a low power, high performance upgrade for the CLC410.
For Military grade product, please refer to the HFA1145/883 data sheet.
Ordering Information
PART NUMBER
(BRAND)
HFA1145IP -40 to 85 8 Ld PDIP E8.3 HFA1145IB
(H1145I) HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps
TEMP. RANGE
(oC) PACKAGE
-40 to 85 8 Ld SOIC M8.15
PKG.
NO.
Features
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 5.8mA
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1M
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 330MHz
• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1000V/µs
• Gain Flatness (to 75MHz) . . . . . . . . . . . . . . . . . . ±0.1dB
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Differential Phase. . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• Output Enable/Disable Time. . . . . . . . . . . . . . 180ns/35ns
• Pin Compatible Upgrade for CLC410
Applications
• Flash A/D Drivers
• Video Switching and Routing
• Professional Video Processing
• Video Digitizing Boards/Systems
• Multimedia Systems
• RGB Preamps
• Medical Imaging
• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications
Pinout
NC
-IN
+IN
V-
HFA1145
(PDIP, SOIC)
TOP VIEW
1 2
-
+
3 4
8
DISABLE
7
V+
6
OUT
5
NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Copyright © Intersil Corporation 1999
Page 2
HFA1145
Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Output Current (Note 1). . . . . . . . . . . . . . . . .Short Circuit Protected
30mA Continuous
60mA 50% Duty Cycle
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >600V
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Output is short circuit protectedto ground. Brief short circuits to ground will not degrade reliability, however continuous (100% dutycycle) output current must not exceed 30mA for maximum reliability.
is measured with the component mounted on an evaluation PC board in free air.
2. θ
JA
Thermal Resistance (Typical, Note 2) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Maximum Junction Temperature (Die Only). . . . . . . . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Electrical Specifications V
= ±5V, AV= +1, RF= 510, RL = 100Ω, Unless Otherwise Specified
SUPPLY
(NOTE 3)
PARAMETER TEST CONDITIONS
TEST
LEVEL
TEMP.
o
(
C) MIN TYP MAX UNITS
INPUT CHARACTERISTICS
Input Offset Voltage A 25 - 2 5 mV
A Full - 3 8 mV Average Input Offset Voltage Drift B Full - 1 10 µV/ Input Offset Voltage
Common-Mode Rejection Ratio
Input Offset Voltage Power Supply Rejection Ratio
= ±1.8V A 25 47 50 - dB
V
CM
= ±1.8V A 85 45 48 - dB
V
CM
= ±1.2V A -40 45 48 - dB
V
CM
= ±1.8V A 25 50 54 - dB
V
PS
= ±1.8V A 85 47 50 - dB
V
PS
= ±1.2V A -40 47 50 - dB
V
PS
Non-Inverting Input Bias Current A 25 - 6 15 µA
A Full - 10 25 µA Non-Inverting Input Bias Current Drift B Full - 5 60 nA/ Non-Inverting Input Bias Current
Power Supply Sensitivity
Non-Inverting Input Resistance V
= ±1.8V A 25 - 0.5 1 µA/V
V
PS
= ±1.8V A 85 - 0.8 3 µA/V
V
PS
= ±1.2V A -40 - 0.8 3 µA/V
V
PS
= ±1.8V A 25 0.8 1.2 - M
CM
= ±1.8V A 85 0.5 0.8 - M
V
CM
= ±1.2V A -40 0.5 0.8 - M
V
CM
Inverting Input Bias Current A 25 - 2 7.5 µA
A Full - 5 15 µA Inverting Input Bias Current Drift B Full - 60 200 nA/ Inverting Input Bias Current
Common-Mode Sensitivity
= ±1.8V A 25 - 3 6 µA/V
V
CM
= ±1.8V A 85 - 4 8 µA/V
V
CM
= ±1.2V A -40 - 4 8 µA/V
V
CM
o
C
o
C
o
C
2
Page 3
HFA1145
Electrical Specifications V
= ±5V, AV= +1, RF= 510, RL = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
(NOTE 3)
PARAMETER TEST CONDITIONS
Inverting Input Bias Current Power Supply Sensitivity
TEST
LEVEL
VPS = ±1.8V A 25 - 2 5 µA/V
= ±1.8V A 85 - 4 8 µA/V
V
PS
= ±1.2V A -40 - 4 8 µA/V
V
PS
TEMP.
o
C) MIN TYP MAX UNITS
(
Inverting Input Resistance C 25 - 60 - Input Capacitance C 25 - 1.6 - pF Input Voltage Common Mode Range
(Implied by V
CMRR, +RIN, and -I
IO
tests)
BIAS
CMS
A 25, 85 ±1.8 ±2.4 - V
A -40 ±1.2 ±1.7 - V
Input Noise Voltage Density (Note 6) f = 100kHz B 25 - 3.5 - nV/ Non-Inverting Input Noise Current Density
f = 100kHz B 25 - 2.5 - pA/
(Note 6) Inverting Input Noise Current Density
f = 100kHz B 25 - 20 - pA/
(Note 6)
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain A AC CHARACTERISTICS R
= 510, Unless Otherwise Specified
F
-3dB Bandwidth
= 0.2V
(V
OUT
P-P
, Note 6)
= -1 C 25 - 500 - k
V
AV = +1, +RS = 510 B 25 - 270 - MHz
B Full - 240 - MHz
= -1, RF = 425 B 25 - 300 - MHz
A
V
= +2 B 25 - 330 - MHz
A
V
B Full - 260 - MHz
= +10, RF = 180 B 25 - 130 - MHz
A
V
B Full - 90 - MHz Full Power Bandwidth
(V 4V
OUT
P-P
= 5V
at AV = +2/-1,
P-P
at AV = +1, Note 6)
Gain Flatness (A
V
= +2, V
OUT
= 0.2V
P-P
, Note 6)
AV = +1, +RS = 510 B 25 - 135 - MHz
= -1 B 25 - 140 - MHz
A
V
= +2 B 25 - 115 - MHz
A
V
To 25MHz B 25 - ±0.03 - dB
B Full - ±0.04 - dB
To 75MHz B 25 - ±0.11 - dB
B Full - ±0.22 - dB Gain Flatness
=+1, +RS=510,V
(A
V
OUT
=0.2V
P-P
,Note 6)
To 25MHz B 25 - ±0.03 - dB
To 75MHz B 25 - ±0.09 - dB Minimum Stable gain A Full - 1 - V/V OUTPUT CHARACTERISTICS A Output Voltage Swing
(Note 6)
Output Current (Note 6)
= +2, RF = 510, Unless Otherwise Specified
V
= -1, RL = 100 A25±3 ±3.4 - V
A
V
= -1, RL = 50 A 25, 85 50 60 - mA
A
V
A Full ±2.8 ±3- V
A -40 28 42 - mA Output Short Circuit Current B 25 - 90 - mA Closed Loop Output Impedance (Note 6) DC B 25 - 0.08 -
Hz Hz
Hz
3
Page 4
HFA1145
Electrical Specifications V
= ±5V, AV= +1, RF= 510, RL = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
(NOTE 3)
PARAMETER TEST CONDITIONS
Second Harmonic Distortion (V
OUT
= 2V
P-P
, Note 6)
Third Harmonic Distortion
= 2V
(V
OUT
Reverse Isolation (S TRANSIENT CHARACTERISTICS A
P-P
, Note 6)
, Note 6) 30MHz B 25 - -55 - dB
12
= +2, RF = 510Ω, Unless Otherwise Specified
V
Rise and Fall Times V
TEST
LEVEL
10MHz B 25 - -48 - dBc 20MHz B 25 - -44 - dBc 10MHz B 25 - -50 - dBc 20MHz B 25 - -45 - dBc
OUT
= 0.5V
P-P
B 25 - 1.1 - ns
TEMP.
o
C) MIN TYP MAX UNITS
(
B Full - 1.4 - ns Overshoot (Note 4)
= 0 to 0.5V, VIN t
(V
OUT
Overshoot (Note 4)
= 0.5V
(V
OUT
P-P
Slew Rate (V
OUT
= 4V
, AV = +1, +RS = 510)
P-P
, VIN t
RISE
RISE
= 1ns)
= 1ns)
+OS B 25 - 3 - %
-OS B 25 - 5 - % +OS B 25 - 3 - %
-OS B 25 - 11 - % +SR B 25 - 1000 - V/µs
B Full - 975 - V/µs
-SR (Note 5) B 25 - 650 - V/µs B Full - 580 - V/µs
Slew Rate
= 5V
(V
OUT
, AV = +2)
P-P
+SR B 25 - 1400 - V/µs
B Full - 1200 - V/µs
-SR (Note 5) B 25 - 800 - V/µs B Full - 700 - V/µs
Slew Rate
= 5V
(V
OUT
, AV = -1)
P-P
+SR B 25 - 2100 - V/µs
B Full - 1900 - V/µs
-SR (Note 5) B 25 - 1000 - V/µs B Full - 900 - V/µs
Settling Time
= +2V to 0V step, Note 6)
(V
OUT
To 0.1% B 25 - 15 - ns To 0.05% B 25 - 23 - ns
To 0.02% B 25 - 30 - ns Overdrive Recovery Time V VIDEO CHARACTERISTICS A
= +2, RF = 510Ω, Unless Otherwise Specified
V
Differential Gain (f = 3.58MHz)
Differential Phase (f = 3.58MHz)
= ±2V B 25 - 8.5 - ns
IN
= 150 B 25 - 0.02 - %
R
L
= 75 B 25 - 0.03 - %
R
L
= 150 B 25 - 0.03 - Degrees
R
L
= 75 B 25 - 0.05 - Degrees
R
L
DISABLE CHARACTERISTICS
Disabled Supply Current V
DISABLE
= 0V A Full - 3 4 mA DISABLE Input Logic Low A Full - - 0.8 V DISABLE Input Logic High A 25, 85 2.0 - - V
A -40 2.4 - - V
DISABLE Input Logic Low Current V
DISABLE
= 0V A Full - 100 200 µA
4
Page 5
HFA1145
Electrical Specifications V
PARAMETER TEST CONDITIONS
DISABLE Input Logic High Current V Output Disable Time (Note 6) V
Output Enable Time (Note 6) V
Disabled Output Capacitance V Disabled Output Leakage V
Off Isolation (V
DISABLE
POWER SUPPLY CHARACTERISTICS
Power Supply Range C 25 ±4.5 - ±5.5 V Power Supply Current (Note 6) A 25 - 5.8 6.1 mA
NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. Undershoot dominates for output signal swings below GND (e.g. 0.5V
5. Slew rates are asymmetrical if theoutput swings below GND (e.g. a bipolar signal). Positiveunipolar output signals have symmetric positive and
6. See Typical Performance Curves for more information.
= 0V, VIN = 1V
condition. See the “Application Information” section for details.
negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details.
P-P
, Note 6)
= ±5V, AV= +1, RF= 510, RL = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
(NOTE 3)
TEST
LEVEL
DISABLE IN
V
DISABLE IN
V
DISABLE DISABLE DISABLE
V
OUT
At 5MHz B 25 - -75 - dB At 25MHz B 25 - -60 - dB
= 5V A Full - 1 15 µA
= ±1V,
= 2.4V to 0V
= ±1V,
= 0V to 2.4V
= 0V B 25 - 2.5 - pF
= 0V, VIN = 2V,
= ±3V
±
), yielding a higher overshoot limit compared to the V
P-P
B 25 - 35 - ns
B 25 - 180 - ns
A Full - 3 10 µA
A Full - 5.9 6.3 mA
TEMP.
o
C) MIN TYP MAX UNITS
(
OUT
= 0 to 0.5V
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedbac k amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and R current feedback amplifiers require a f eedback resistor, even for unity gain applications, and R
, in conjunction with the
F
internal compensation capacitor,sets the dominant pole ofthe frequency response. Thus, the amplifier’ s bandwidth is inverselyproportional toR for R
= 510 at a gain of +2. Decreasing RF decreases
F
. The HFA1145design isoptimized
F
stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains, however, the amplifier is more stable so R be decreased in a trade-off of stability for bandwidth.
The table below lists recommended R
values for various
F
gains, and the expected bandwidth. For a gain of +1, a resistor (
+R
) in series with +IN is required to reduce gain
S
peaking and increase stability.
F
can
F
. All
GAIN (ACL) R
-1 425 300 +1 510 (+RS = 510Ω) 270 +2 510 330 +5 200 300
+10 180 130
()
F
BANDWIDTH
(MHz)
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the non-inverting input should be 50Ω. This is especially important in inverting gain configurations where the non­inverting input would normally be connected directly to GND.
DISABLE Input TTL Compatibility
The HFA1145 derives an internal GND reference for the digital circuitry as long as the power supplies are symmetrical about GND. With symmetrical supplies the digital switching threshold (V
0.8)/2) is 1.4V, which ensures the TTL compatibility of the DISABLE input. If asymmetrical supplies (e.g. +10V,0V) are utilized, the switching threshold becomes:
V+ V-+
V
------------------- 1.4V+=
TH
and the V
2
and VIL levels will be VTH± 0.6V, respectively.
IH
= (VIH + VIL)/2 = (2.0 +
TH
5
Page 6
HFA1145
Optional GND Pad (Die Use Only) for TTL Compatibility
The die version of the HFA1145 provides the user with a GND pad for setting the disable circuitry GND reference. With symmetrical supplies the GND pad may be left unconnected, or tied directly to GND. If asymmetrical supplies (e.g. +10V, 0V) are utilized, and TTL compatibility is desired, die users must connect the GND pad to GND. With an external GND, the DISABLE input is TTL compatible regardless of supply voltage utilized.
Pulse Undershoot and Asymmetrical Slew Rates
The HF A1145 utiliz es a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor . The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging belo w ground, and an increased undershoot on the negative portion of the output wavef orm (See Figures 5, 8, and 11). This undershoot isn’t present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates f or output signals with a negative voltage component. The slew r ate degradesas theoutput signalcrosses through0V (SeeFigures 5, 8, and 11), resulting in a slower over all negativ e sle w rate . Positiv e only signals ha v e symmetrical slew r ates as illustrated in the large signal positivepulse response graphs (See Figures 4, 7, and 10).
PC Board Layout
This amplifier’s frequency response depends greatly on the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must!
Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the device’s input and output connections. Capacitance, parasitic or planned, connected to the output must be minimized, or isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input (-IN), as this capacitance causes gain peaking, pulse overshoot, and if large enough, instability. To reduce this capacitance, the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible.
An example of a good high frequency lay out is theEvaluation Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (R
) in series with the output
S
prior to the capacitance. Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
and C
S
L
combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdampedresponse, while points below or left of the curve indicate areas of underdamped performance.
R
and CLform a low pass network at the output, thus limiting
S
system bandwidth well below the amplifier bandwidth of 270MHz (for A
= +1). By decreasing RSas CLincreases (as
V
illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, the bandwidth decreases as the load capacitance increases.For example, at A
= +1, RS = 62, CL= 40pF, the overall bandwidth is
V
limited to 180MHz, and bandwidth drops to 75MHz at A
= +1, RS = 8, CL= 400pF.
V
50
40
30
20
10
SERIES OUTPUT RESISTANCE ()
0
0 100 200 300 400
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
AV = +1
AV = +2
150 250 35050
LOAD CAPACITANCE (pF)
Evaluation Board
The performance of the HFA1145 may be evaluated using the HFA11XX Evaluation Board.
The layout and schematic of the board are shown in Figure
2. The V pin, but note that this connection has no 50 order evaluation boards (part number HFA11XXEVAL), please contact your local sales office.
connection may be used to exercise the DISABLE
H
termination. To
6
Page 7
+IN
HFA1145
V
H
1
OUT
V
L
V+
V-
GND
FIGURE 2A. TOP LAYOUT
IN
10µF
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
T ypical Performance Curves V
200
AV = +1
= 510
+R
150
100
-50
S
50
0
FIGURE 2B. TOP LAYOUT
510 510
R
1
1
50
0.1µF
SUPPLY
2 3 4
-5V
GND
= ±5V, RF = 510Ω, TA = 25oC, RL = 100Ω,Unless Otherwise Specified
V
H
8
0.1µF
7
50
6 5
GND
3.0
2.5
2.0
1.5
1.0
0.5
10µF
OUT V
L
AV = +1 +RS = 510
+5V
0
-100
OUTPUT VOLTAGE (mV)
-150
-200 TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
-0.5
-1.0 TIME (5ns/DIV.)
FIGURE 3. SMALL SIGNAL PULSE RESPONSE FIGURE 4. LARGE SIGNAL POSITIVE PULSE RESPONSE
7
Page 8
HFA1145
T ypical Performance Curves V
2.0 AV = +1
+RS = 510
1.5
1.0
0.5
0
-0.5
-1.0
OUTPUT VOLTAGE (V)
-1.5
-2.0 TIME (5ns/DIV.)
= ±5V, RF = 510Ω, TA = 25oC, RL = 100Ω,Unless Otherwise Specified (Continued)
SUPPLY
200
AV = +2
150
100
50
0
-50
-100
OUTPUT VOLTAGE (mV)
-150
-200 TIME (5ns/DIV.)
FIGURE 5. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 6. SMALL SIGNAL PULSE RESPONSE
3.0 AV = +2 AV = +2
2.5
2.0
1.5
2.0
1.5
1.0
0.5
OUTPUT VOLTAGE (V)
-0.5
-1.0
0
TIME (5ns/DIV.)
1.0
0.5
-0.5
-1.0
OUTPUT VOLTAGE (V)
-1.5
-2.0
0
TIME (5ns/DIV.)
FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 8. LARGE SIGNAL BIPOLAR PULSE RESPONSE
200
150
100
50
0
-50
-100
OUTPUT VOLTAGE (mV)
AV = +10 R
= 180
F
3.0
2.5
2.0
1.5
1.0
0.5
OUTPUT VOLTAGE (V)
0
AV = +10 R
= 180
F
-150
-200 TIME (5ns/DIV.)
-0.5
-1.0 TIME (5ns/DIV.)
FIGURE 9. SMALL SIGNAL PULSE RESPONSE FIGURE 10. LARGE SIGNAL POSITIVE PULSE RESPONSE
8
Page 9
HFA1145
T ypical Performance Curves V
2.0 AV = +10
R
1.5
1.0
0.5
-0.5
OUTPUT VOLTAGE (V)
-1.0
-1.5
-2.0
= 180
F
0
TIME (5ns/DIV.)
= ±5V, RF = 510Ω, TA = 25oC, RL = 100Ω,Unless Otherwise Specified (Continued)
SUPPLY
DISABLE
800mV/DIV.
(0.4V to 2.4V)
OUT
400mV/DIV.
0V
AV = +1, VIN= 1V
TIME (50ns/DIV.)
FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 12. OUTPUT ENABLE AND DISABLE RESPONSE
V
= 200mV
+RS = 510 (+1)
3
+R
0
GAIN (dB)
-3
OUT
= 0 (-1)
S
P-P
AV = +1
AV = -1
3
0
-3
AV = +10
AV = +5
AV = +2
0.3 1 10 100 500 FREQUENCY (MHz)
FIGURE 13. FREQUENCY RESPONSE
AV = +2
3 0
-3
NORMALIZED GAIN (dB)
0.3 1 10 100 500
V
OUT
V
OUT
V
= 1.5V
OUT
FREQUENCY (MHz)
= 1.5V
= 5V
V
OUT
V
OUT
P-P P-P
= 200mV
P-P
V
OUT
= 200mV
P-P
= 5V
AV = -1
AV = +1
P-P
P-P
NORMALIZED GAIN (dB)
0
90 180
270
NORMALIZED PHASE (DEGREES)
0.3 1 10 100 500
3 0
-3
0 90 180
270
PHASE (DEGREES)
NORMALIZED GAIN (dB)
V
= 200mV
OUT
RF = 510 (+2) R
= 200 (+5)
F
R
= 180 (+10)
F
P-P
FREQUENCY (MHz)
AV = +5
AV = +2
AV = +10
0
90 180
270
FIGURE 14. FREQUENCY RESPONSE
AV = -1
V
= 4V = 5V
(+1)
P-P
(-1, +2)
P-P
FREQUENCY (MHz)
AV = +1
AV = +2
OUT
V
OUT
= 510(+1)
+R
S
1 10 100 200
PHASE (DEGREES)
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUSOUTPUT
VOLTAGES
9
FIGURE 16. FULL POWER BANDWIDTH
Page 10
HFA1145
T ypical Performance Curves V
V
= 200mV
OUT
3
AV = +2
0
-3
NORMALIZED GAIN (dB)
0.3 1 10 100 500
P-P
FREQUENCY (MHz)
RL = 500
RL = 50
RL = 100
RL = 100
RL = 1k RL = 500
= ±5V, RF = 510Ω, TA = 25oC, RL = 100Ω,Unless Otherwise Specified (Continued)
SUPPLY
RL = 1k
RL = 50
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUSLOAD
RESISTORS
V
= 200mV
OUT
+RS = 510 (+1)
0.25
0.20
0.15
0.10
0.05 0
-0.05
NORMALIZED GAIN (dB)
-0.10
P-P
AV = +2
AV = +1
0 90 180 270
PHASE (DEGREES)
500
400
300
200
BANDWIDTH (MHz)
100
0
-100 -50 0 50 100 150
AV = +2
= +1
A
V
= +10
A
V
TEMPERATURE (oC)
V
= 200mV
OUT
RF = 180 (+10) +RS = 510 (+1)
FIGURE 18. -3dB BANDWIDTH vs TEMPERATURE
-30 AV = +2
-40
V
= 1V
IN
P-P
-50
-60
-70
-80
OFF ISOLATION (dB)
-90
P-P
11075
FREQUENCY (MHz)
FIGURE 19. GAIN FLATNESS FIGURE 20. OFF ISOLATION
-40 V
= 2V
OUT
-50
-60
-70
-80
-90
REVERSE ISOLATION (dB)
0.3 1 10 100
P-P
FREQUENCY (MHz)
AV = +1, +2
AV = -1
OUTPUT IMPEDANCE ()
100
0.01
FIGURE 21. REVERSE ISOLATION (S12)
10
0.3 1 10 100 FREQUENCY (MHz)
AV = +2
1K
10
1
0.1
0.3 1 10 100 FREQUENCY (MHz)
1000
FIGURE 22. ENABLED OUTPUT IMPEDANCE
Page 11
HFA1145
T ypical Performance Curves V
0.8
0.6
0.4
0.2
0.1 0
-0.2
-0.4
SETTLING ERROR (%)
-0.6
-0.8
3 8 13 18 23 28 33 38 43 48
TIME (ns)
SUPPLY
FIGURE 23. SETTLING RESPONSE FIGURE 24. SECOND HARMONIC DISTORTION vs P
-30 AV = +2
-40
20MHz
-50
DISTORTION (dBc)
-60
-70
-5 0 5 10 15 OUTPUT POWER (dBm)
10MHz
= ±5V, RF = 510Ω, TA = 25oC, RL = 100Ω,Unless Otherwise Specified (Continued)
-30 AV = +2
-40
20MHz
-50
10MHz
DISTORTION (dBc)
-60
-70
-5 0 5 10 15 OUTPUT POWER (dBm)
3.6 A
= -1
V
3.5
3.4
3.3
3.2
3.1
3.0
2.9
OUTPUT VOLTAGE (V)
2.8
2.7
2.6
-50 -25 0 25 50 75 100 125
+V
+V
OUT
OUT
|-V
| (RL= 100Ω)
OUT
(RL= 100Ω)
(RL= 50Ω)
|-V
OUT
TEMPERATURE (
| (RL= 50Ω)
o
C)
V
OUT
AV = +2
= 2V
OUT
FIGURE 25. THIRD HARMONIC DISTORTION vs P
100
10
NOISE VOLTAGE (nV/Hz)
1
0.1 1 10 100 FREQUENCY (kHz)
I
NI+
OUT
100
I
NI-
E
NI
Hz)
10
NOISE CURRENT (pA/
1
FIGURE 26. OUTPUT VOLTAGE vs TEMPERATURE
6.1
6.0
5.9
5.8
5.7
POWER SUPPLY CURRENT (mA)
5.6
3.5 4 4.5 5 5.5 6 6.5 7 7.5
POWER SUPPLY VOLTAGE (±V)
FIGURE 27. INPUT NOISE CHARACTERISTICS FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE
11
Page 12
Die Characteristics
HFA1145
DIE DIMENSIONS:
59 mils x 59 mils x 19 mils 1500µm x 1500µm x 483µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8k
Å ±0.4kÅ
Type: Metal 2: AICu(2%) Thickness: Metal 2: 16k
Å ±0.8kÅ
Metallization Mask Layout
-IN
HFA1145
PASSIVATION:
Type: Nitride Thickness: 4k
Å ±0.5kÅ
TRANSISTOR COUNT:
75
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
DISABLE
V+
OUT
+IN
V-
OPTIONAL GND (NOTE)
NOTE: This pad is notbonded out on packaged units. Die users mayset a GNDreference,via thispad,to ensure the TTL compatibility of the DIS input when using asymmetrical supplies (e.g. V+ = 10V, V- = 0V). See the “Application Information” section for details.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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