330MHz, Low Power, Current Feedback
Video Operational Amplifier
The HFA1105 is a high speed, low power current feedback
amplifier built with Intersil’s proprietary complementary
bipolar UHF-1 process.
This amplifier features an excellent combination of low
power dissipation (58mW) and high performance. The slew
rate, bandwidth, and low output impedance (0.08Ω) make
this amplifier a good choice for driving Flash ADCs.
Component and composite video systems also benefit from
this op amp’s excellent gain flatness, and good differential
gain and phase specifications. The HFA1105 is ideal for
interfacing to Intersil’s line of video crosspoint switches
(HA4201, HA4600, HA4314, HA4404, HA4344), to create
high performance, low power switchers and routers.
The HFA1105 is a low power, high performance upgrade for
the CLC406. For a comparable amplifier with output disable
or output limiting functions, please see the data sheets for
the HFA1145 and HFA1135 respectively.
For Military grade product, please refer to the HFA1145/883
data sheet.
Ordering Information
PART NUMBER
(BRAND)
HFA1105IP-40 to 858 Ld PDIPE8.3
HFA1105IB
(H1105I)
HFA11XXEVALDIP Evaluation Board for High Speed
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Inverting Input ResistanceC25-60-Ω
Input CapacitanceC25-1.6-pF
Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN, and -I
CMS Tests)
BIAS
A25, 85±1.8±2.4-V
A-40±1.2±1.7-V
Input Noise Voltage Density (Note 6)f = 100kHzB25-3.5-nV/√Hz
Non-Inverting Input Noise Current Density (Note 6)f = 100kHzB25-2.5-pA/√Hz
Inverting Input Noise Current Density (Note 6)f = 100kHzB25-20-pA/√Hz
20MHzB25--45-dBc
Reverse Isolation (S12, Note 6)30MHzB25--55-dB
TRANSIENT CHARACTERISTICS AV = +2, RF = 510Ω, Unless Otherwise Specified
Rise and Fall TimesV
OUT
= 0.5V
P-P
B25-1.1-ns
BFull-1.4-ns
3
Page 4
HFA1105
Electrical Specifications V
PARAMETERTEST CONDITIONS
Overshoot (Note 4)
(V
= 0 to 0.5V, VIN t
OUT
Overshoot (Note 4)
(V
= 0.5V
OUT
Slew Rate
(V
= 4V
OUT
Slew Rate
(V
= 5V
OUT
Slew Rate
(V
= 5V
OUT
Settling Time
(V
= +2V to 0V step, Note 6)
OUT
Overdrive Recovery TimeVIN = ±2VB25-8.5-ns
VIDEO CHARACTERISTICSAV = +2, RF = 510Ω, Unless Otherwise Specified
Differential Gain
(f = 3.58MHz)
Differential Phase
(f = 3.58MHz)
POWER SUPPLY CHARACTERISTICS
Power Supply RangeC25±4.5-±5.5V
Power Supply Current (Note 6)A25-5.86.1mA
NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. Undershoot dominates for output signal swings below GND (e.g., 0.5V
condition. See the “Application Information” section for details.
5. Slew rates are asymmetrical if the output swings belowGND(e.g.abipolarsignal). Positive unipolar output signals have symmetric positive and
negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details.
6. See Typical Performance Curves for more information.
), yielding a higher overshoot limit compared to the V
P-P
TEMP.
(oC)MINTYPMAXUNITS
OUT
= 0 to 0.5V
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
4
amplifier’s unique relationship between bandwidth and R
.
F
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and R
, in conjunction with
F
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to R
optimized for R
= 510Ω at a gain of +2. Decreasing R
F
. The HFA1105 design is
F
F
decreases stability, resulting in excessive peaking and
Page 5
HFA1105
overshoot (Note: Capacitive feedback will cause the same
problemsdue to the feedbackimpedance decrease at higher
frequencies). At higher gains, however, the amplifier is more
stable so R
can be decreased in a trade-off of stability for
F
bandwidth.
The table below lists recommended R
values for various
F
gains, and the expected bandwidth. For a gain of +1, a
resistor (
+R
) in series with +IN is required to reduce gain
S
peaking and increase stability.
GAIN
(ACL)R
-1425300
+1510 (+RS = 510Ω)270
+2510330
+5200300
+10180130
(Ω)
F
BANDWIDTH
(MHz)
Non-Inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be ≥50Ω. This is especially
important in inverting gain configurations where the noninverting input would normally be connected directly to GND.
Pulse Undershoot and Asymmetrical Slew Rates
The HFA1105 utilizes a quasi-complementary output stage to
achievehighoutput current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added
distortion for signals swinging below ground, and an
increased undershoot on the negative portion of the output
waveform (See Figures 5, 8, and 11). This undershoot isn’t
present for small bipolar signals, or large positive signals.
Another artifact of the composite device is asymmetrical slew
rates for output signals with a negative voltage component.
The slew rate degrades as the output signal crosses through
0V (See Figures 5, 8, and 11), resulting in a slower overall
negative slew rate. Positive only signals have symmetrical
slew rates as illustrated in the large signal positive pulse
response graphs (See Figures 4, 7, and 10).
Terminated microstrip signal lines are recommended at the
device’s input and output connections. Capacitance,
parasitic or planned, connected to the output must be
minimized, or isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to
ground at the amplifier’s inverting input (-IN), as this
capacitance causes gain peaking, pulse overshoot, and if
large enough, instability. To reduce this capacitance, the
designer should remove the ground plane under traces
connected to
-IN, and keep connections to -IN as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdampedresponse,while points below or left of the curve
indicate areas of underdamped performance.
R
and CLform a low pass network at the output, thus limiting
S
system bandwidth well below the amplifier bandwidth of
270MHz (for A
= +1). By decreasing RSas CLincreases (as
V
illustrated in the curves), the maximum bandwidth is obtained
without sacrificing stability. In spite of this, the bandwidth
decreases as the load capacitance increases. For example, at
A
= +1, RS=62Ω,CL= 40pF, the overallbandwidth is limited
V
to 180MHz, and bandwidth drops to 75MHz at A
R
=8Ω, CL = 400pF.
S
) in series with the output
S
and C
S
= +1,
V
L
PC Board Layout
The amplifier’s frequency response depends greatly on the
care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
5
Page 6
HFA1105
50
40
30
20
10
SERIES OUTPUT RESISTANCE (Ω)
0
0100200300400
LOAD CAPACITANCE (pF)
AV = +1
AV = +2
15025035050
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1105 may be evaluated using
the HFA11XX Evaluation Board.
The layout and schematic of the board are shown in Figure
2. To order evaluationboards (part number HFA11XXEVAL),
please contact your local sales office.
10µF
510510
R
1
50Ω
IN
0.1µF
-5V
1
2
3
4
8
7
6
5
GND
0.1µF
50Ω
V
H
GND
OUT
V
L
10µF
+5V
FIGURE 2C. SCHEMATIC
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
V
H
1
+IN
FIGURE 2A. TOP LAYOUT
OUT
V
L
V+
V-
GND
FIGURE 2B. BOTTOM LAYOUT
6
Page 7
HFA1105
T ypical P erf ormance Curves
200
AV = +1
+R
= 510Ω
150
100
-50
-100
OUTPUT VOLTAGE (mV)
-150
-200
2.0
1.5
1.0
S
50
0
TIME (5ns/DIV.)
FIGURE 3. SMALL SIGNAL PULSE RESPONSEFIGURE 4. LARGE SIGNAL POSITIVE PULSE RESPONSE
59 mils x 59 mils x 19 mils
1500µm x 1500µm x 483µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8k
Å ±0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16k
Å ±0.8kÅ
Metallization Mask Layout
-IN
HFA1105
Type: Nitride
Thickness: 4k
Å ±0.5kÅ
TRANSISTOR COUNT:
75
SUBSTRATE POTENTIAL (Powered Up):
Floating
(Recommend Connection to V-)
NC
V+
OUT
+IN
V-
NC
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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