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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4731B; HEF4731V
LSI
Quadruple 64-bit static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Quadruple 64-bit static shift register
DESCRIPTION
The HEF4731B and HEF4731V are quadruple 64-bit static
shift registers each with separate serial data inputs (DAto
DD), clock inputs (CPAto CPD) and data outputs (O
O
) from the 64th register position.
63D
63A
to
HEF4731B; HEF4731V
LSI
Recommended supply voltage range for HEF4731B is 3 to
15 V and for HEF4731V is 4,5 to 12,5 V.
Data are shifted to the next stage on the negative-going
transitions of the clock. Low impedance outputs are
provided for direct interface to TTL.
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4731BP;
HEF4731VP(N):
HEF4731BD;
HEF4731VD(F):
( ): Package Designator North America
FAMILY DATA, IDDLIMITS category LSI
See Family Specifications
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
January 1995 2
Page 3
Philips Semiconductors Product specification
Quadruple 64-bit static shift register
Fig.3 Logic diagram (one of 64-bits shift register).
The values given at VDD= 15 V in the following DC
and AC characteristics, are not applicable to the HEF4731V,
because of its reduced supply voltage range.
HEF4731B; HEF4731V
LSI
DC CHARACTERISTICS
= 0 V; VI=VSSor V
V
SS
DD
T
(°C)
amb
V
V
DD
V
V
OL
V
OH
V
SYMBOL
−40 + 25 + 85
MIN. MAX. MIN. MAX. MIN. MAX.
Output (source) 5 2,5 3 2,5 2,0 mA
current 5 4,6
HIGH 10 9,5 3 2,5 2,0 mA
−I
OH
1 0,85 0,65 mA
15 13,5 10 8,5 6,5 mA
Output (sink) 4,75 0,4 2,3 2,0 1,6 mA
current 10 0,5 I
OL
6,0 5,0 4,0 mA
LOW 15 1,5 20,0 18,0 14,0 mA
AC CHARACTERISTICS
= 0 V; T
V
SS
Dynamic power 5 13 000 f
dissipation per 10 55 000 f
package (P) 15 140 000 f
=25°C; input transition times ≤ 20 ns
amb
V
DD
V
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
) = sum of outputs
∑ (f
oCL
V
= supply voltage (V)
DD
January 1995 3
Page 4
Philips Semiconductors Product specification
Quadruple 64-bit static shift register
HEF4731B; HEF4731V
AC CHARACTERISTICS
= 0 V; T
V
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
Transition times O
HIGH to LOW 10 t
LOW to HIGH 10 t
Minimum clock 5 200 80 ns
pulse width; HIGH 10 t
Set-up time 5 25 −5ns
D→
CP 10 t
Hold time 5 50 20 ns
D →
CP 10 t
Maximum clock 5 2.25 6 MHz Note: the maximum
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
63
SYMBOL MIN. TYP. MAX.
5 115 230 ns 132 ns + (0,26 ns/pF) C
PHL
15 40 80 ns 34 ns + (0,11 ns/pF) C
5 130 260 ns 138 ns + (0,45 ns/pF) C
PLH
15 45 90 ns 39 ns + (0,13 ns/pF) C
63
5 30 60 ns 10 ns + (0,40 ns/pF) C
THL
15 10 20 ns 3 ns + (0,13 ns/pF) C
5 40 80 ns 8 ns + (0,65 ns/pF) C
TLH
15 15 30 ns 5 ns + (0,20 ns/pF) C
WCPH
75 30 ns
15 50 20 ns
su
15 −5ns
15 15 −5ns
hold
30 10 ns
15 20 5 ns
max
6 16 MHz power dissipation has
15 9 25 MHz to be observed
TYPICAL EXTRAPOLA TION
FORMULA
55 110 ns 47 ns + (0,16 ns/pF) C
65 130 ns 56 ns + (0,19 ns/pF) C
12 24 ns 3 ns + (0,18 ns/pF) C
20 40 ns 5 ns + (0,30 ns/pF) C
see also waveforms Fig.4
LSI
L
L
L
L
L
L
L
L
L
L
L
L
Fig.4 Waveforms showing
minimum clock pulse
width, set-up and hold
times for D to CP.
Set-up and hold times
are shown as positive
values but may be
specified as negative
values.
January 1995 4
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