Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4526B
MSI
Programmable 4-bit binary down
counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
DESCRIPTION
The HEF4526B is a synchronous programmable 4-bit
binary down counter with an active HIGH and an active
LOW clock input (CP0, CP1), an asynchronous parallel
load input (PL), four parallel inputs (P0to P3), a cascade
feedback input (CF), four buffered parallel outputs (O0to
O3), a terminal count output (TC) and an overriding
asynchronous master reset input (MR).
This device is a programmable, cascadable down counter
with a decoded TC output for divide-by-n applications. In
single stage applications the TC output is connected to PL.
CF allows cascade divide-by-n operation with no
additional gates required.
Information on P
0
to P3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
MR, which must be LOW. When PL andCP1are LOW, the
counter advances on a LOW to HIGH transition of CP0.
When PL is LOW and CP0 is HIGH, the counter advances
on a HIGH to LOW transition of CP1. TC is HIGH when the
counter is in the zero state (O0=O1=O2=O3= LOW)
and CF is HIGH and PL is LOW. A HIGH on MR resets the
counter (O0to O3= LOW) independent of other input
conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
Page 3
January 1995 3
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
Fig.2 Pinning diagram.
HEF4526BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4526BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4526BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
PL parallel load input
P
0
to P
3
parallel inputs
CF cascade feedback input
CP
0
clock input (LOW to HIGH, triggered)
CP
1
clock input (HIGH to LOW, triggered)
MR asynchronous master reset input
TC terminal count output
O
0
to O
3
buffered parallel outputs
COUNTING MODE
CF = HIGH; PL = LOW; MR = LOW
COUNT
OUTPUTS
O
3
O
2
O
1
O
0
15 H H H H
14 H H H L
13 H H L H
12 H H L L
11 H L H H
10 H L H L
9HLLH
8HLLL
7LHHH
6LHHL
5LHLH
4LHLL
3LLHH
2LLHL
1LLLH
0LLLL
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
MR PL CP
0
CP
1
MODE
H X X X reset (asynchronous)
L H X X preset (asynchronous)
L L H no change
L L L no change
L L X no change
L L X no change
L L L counter advances
L L H counter advances
Page 4
January 1995 4
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
SINGLE STAGE OPERATION
Divide-by-n; MR = LOW; CF = HIGH;
CP1= LOW
PL P
3P2
P
1
P
0
DIVIDEBYTC OUTPUT
PULSE WIDTH
LXXX X 16
one clock
period
TC H H H H 15
clock pulse
HIGH
TC H H H L 14
TC H H L H 13
TC H H L L 12
TC H L H H 11
TC H L H L 10
TC H L L H 9
TC H L L L 8
TC L H H H 7
TC L H H L 6
TC L H L H 5
TC L H L L 4
TC L L H H 3
TC L L H L 2
TC L L L H 1
TC L L L L no operation
Fig.3 State diagram.
Page 5
January 1995 5
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
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Fig.4 Logic diagram.
Page 6
January 1995 6
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; input transition times ≤ 20 ns
AC CHARACTERISTICS
V
SS
=0V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 1000 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 4000 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 10 000 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load capacitance (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
V
DD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP0, CP1→ O
n
5 150 300 ns 123 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
65 130 ns 54 ns + (0,23 ns/pF) C
L
15 50 100 ns 42 ns + (0,16 ns/pF) C
L
5 150 300 ns 123 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
65 130 ns 54 ns + (0,23 ns/pF) C
L
15 50 100 ns 42 ns + (0,16 ns/pF) C
L
CP0, CP1→ TC 5 210 420 ns 183 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
90 180 ns 79 ns + (0,23 ns/pF) C
L
15 70 140 ns 62 ns + (0,16 ns/pF) C
L
5 210 420 ns 183 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
90 180 ns 79 ns + (0,23 ns/pF) C
L
15 70 140 ns 62 ns + (0,16 ns/pF) C
L
PL → O
n
5 200 400 ns 173 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
80 160 ns 69 ns + (0,23 ns/pF) C
L
15 60 120 ns 52 ns + (0,16 ns/pF) C
L
5 180 360 ns 153 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
70 140 ns 59 ns + (0,23 ns/pF) C
L
15 50 100 ns 42 ns + (0,16 ns/pF) C
L
MR → O
n
5 140 280 ns 113 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
55 110 ns 44 ns + (0,23 ns/pF) C
L
15 40 80 ns 32 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
Page 7
January 1995 7
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
AC CHARACTERISTICS
V
SS
=0V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
Note
1. In the divide-by-n mode (PL connected to TC), one has to observe the maximum HIGH to LOW propagation delay
for CP to TC, before applying the next clock pulse.
V
DD
V
SYMBOL MIN. TYP. MAX.
Minimum clock 5 80 40 ns
see also waveforms
Figs 5 and 6
pulse width CP
0
10 t
WCPL
40 20 ns
LOW 15 30 15 ns
Minimum clock 5 80 40 ns
pulse width
CP
1
10 t
WCPH
40 20 ns
HIGH 15 30 15 ns
Minimum PL 5 100 50 ns
pulse width; HIGH 10 t
WPLH
40 20 ns
15 32 16 ns
Minimum MR 5 130 65 ns
pulse width; HIGH 10 t
WMRH
50 25 ns
15 40 20 ns
Hold time 5 30 5 ns
P
n
→ PL 10 t
hold
20 5 ns
15 15 5 ns
Set-up time 5 30 0 ns
P
n
→ PL 10 t
su
20 0 ns
15 15 0 ns
Maximum clock 5 6 12 MHz
see note 1pulse frequency 10 f
max
12 25 MHz
PL = LOW 15 16 32 MHz
Page 8
January 1995 8
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
Fig.5 Waveforms showing minimum PL pulse width, propagation delays for PL, Pnto Onand hold time for PL
to Pn.
Fig.6 Waveforms showing minimum CP0and CP1pulse widths, propagation delays for CP0, CP1to Onand TC.
Page 9
January 1995 9
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
APPLICATION INFORMATION
Some examples of applications for the HEF4526B are:
• Divide-by-n counter
• Programmable frequency divider
Fig.7 Typical application of two HEF4526B circuits in a 2-stage programmable down counter (one cycle). S are
thumbwheel switches; when open: LOW state.
Counting cycle:
Page 10
January 1995 10
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
Fig.8 Typical application of two HEF4526B circuits in a 2-stage programmable frequency divider. S are
thumbwheel switches; when open: LOW state.
Counting cycle:
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