Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4521B
MSI
24-stage frequency divider and
oscillator
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
DESCRIPTION
The HEF4521B consists of a chain of 24 toggle flip-flops
with an overriding asynchronous master reset input (MR),
and an input circuit that allows three modes of operation.
The single inverting stage (I2/O2) will function as a crystal
oscillator, or in combination with I1as an RC oscillator, or
as an input buffer for an external oscillator. Low-power
operation as a crystal oscillator is enabled by connecting
external resistors to pins 3 (V
SS
’) and 5 (VDD’).
Each flip-flop divides the frequency of the previous flip-flop
by two, consequently the HEF4521B will count up to
224= 16777216. The counting advances on the HIGH to
LOW transition of the clock (I2). The outputs of the last
seven stages are available for additional flexibility.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
Page 3
January 1995 3
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
HEF4521BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4521BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4521BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
COUNT CAPACITY
OUTPUT COUNT CAPACITY
O
18
218= 262 144
O
19
219= 524 288
O
20
220= 1 048 576
O
21
221= 2 097 152
O
22
222= 4 194 304
O
23
223= 8 388 608
O
24
224= 16 777 216
FUNCTIONAL TEST SEQUENCE
INPUTS
CONTROL
TERMINALS
OUTPUTS
REMARKS
MR I
2
O
2
VSS’V
DD
’O
18
to O
24
HLLVDDV
SS
L counter is in three 8-stage sections
in parallel mode; I2and O2are
interconnected (O2is now input);
counter is reset by MR
LV
DD
V
SS
H 255 pulses are clocked into I2,O
2
(the counter advances on the LOW
to HIGH transition)
LLLV
SS
V
SS
HV
SS
’ is connected to V
SS
LHLVSSV
SS
H the input I2is made HIGH
LHLV
SS
V
DD
HV
DD
’ is connected to VDD;O2is
now made floating and becomes an
output; the device is now in the
224mode
LV
SS
V
DD
L
counter ripples from an all HIGH
state to an all LOW state
A test function has been included for the reduction of the
test time required to exercise all 24 counter stages. This
test function divides the counter into three 8-stage
sections by connecting VSS’toVDDand VDD’toVSS. Via
I2(connected to O2) 255 counts are loaded into each of
the 8-stage sections in parallel. All flip-flops are now at a
HIGH state.
The counter is now returned to the normal 24-stage in
series configuration by connecting VSS’ to VSSand VDD’to
VDD. One more pulse is entered into input I2, which will
cause the counter to ripple from an all HIGH state to an all
LOW state.
Page 4
January 1995 4
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
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Fig.3 Logic diagram; for schematic diagram of clock circuit see Fig.4.
Page 5
January 1995 5
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
V
DD
V SYMBOL MIN. TYP. MAX.
TYPICAL
EXTRAPOLATION
FORMULA
Propagation delays
I2→ O
18
5 950 1900 ns 923 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
350 700 ns 339 ns + (0,23 ns/pF) C
L
15 220 440 ns 212 ns + (0,16 ns/pF) C
L
5 950 1900 ns 923 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
350 700 ns 339 ns + (0,23 ns/pF) C
L
15 220 440 ns 212 ns + (0,16 ns/pF) C
L
On→ On+ 1 5 40 80 ns 13 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
15 30 ns 4 ns + (0,23 ns/pF) C
L
15 10 20 ns 2 ns + (0,16 ns/pF) C
L
5 40 80 ns 13 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
15 30 ns 4 ns + (0,23 ns/pF) C
L
15 10 20 ns 2 ns + (0,16 ns/pF) C
L
MR → O
n
5 120 240 ns 93 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
55 110 ns 44 ns + (0,23 ns/pF) C
L
15 40 80 ns 32 ns + (0,16 ns/pF) C
L
I1→ O
1
5 90 180 ns 63 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
35 70 ns 24 ns + (0,23 ns/pF) C
L
15 25 50 ns 17 ns + (0,16 ns/pF) C
L
5 60 120 ns 33 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
30 60 ns 19 ns + (0,23 ns/pF) C
L
15 20 40 ns 12 ns + (0,16 ns/pF) C
L
Fig.4 Schematic diagram of clock input circuitry.
Page 6
January 1995 6
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
V
DD
V
SYMBOL MIN. TYP. MAX.
Minimum I
2
pulse 5 80 40 ns
see also waveforms
Fig.5
width; HIGH 10 t
WI2H
40 20 ns
15 30 15 ns
Minimum MR 5 70 35 ns
pulse width; HIGH 10 t
WMRH
40 20 ns
15 30 15 ns
Recovery time 5 20 −10 ns
for MR 10 t
RMR
15 −5ns
15 15 0 ns
Maximum clock 5 6 12 MHz
pulse frequency 10 f
max
12 25 MHz
15 17 35 MHz
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 1 200 f
i
+∑ (foCL) × V
DD
2
where
dissipation per 10 5 100 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 13 050 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load capacitance (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
V
DD
V SYMBOL MIN. TYP. MAX.
TYPICAL
EXTRAPOLATION
FORMULA
Page 7
January 1995 7
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
Fig.5 Waveforms showing minimum pulse widths for MR and I2, recovery time for MR.
Page 8
January 1995 8
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
APPLICATION INFORMATION
Typical characteristics for crystal oscillator circuit (Fig.6):
500 kHz
CIRCUIT
50 kHz
CIRCUIT
UNIT
Crystal characteristics
resonance frequency 500 50 kHz
crystal cut S N −
equivalent resistance; R
S
1 6,2 kΩ
External resistor/capacitor values
R
o
47 750 kΩ
C
T
82 82 pF
C
S
20 20 pF
Fig.6 Crystal oscillator circuit.
(1) Optional for low power operation.
Page 9
January 1995 9
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
Fig.7 RC oscillator circuit;
f in Hz, R in Ω, C in F.
f
1
2,3 R
TC
C××
------------------------------------
;R
S
2RTCin which:,≥≈
R
SRTC
V
IL max
I
LI
------------------
<+
maximum input voltage LOW()
input leakage current()
Fig.8 Oscillator frequency as a
function of RTCand C;
VDD= 10 V; test circuit is
Fig.7.
RTC; C = 1 nF; RS≈ 2 R
TC
C; RTC= 56 kΩ; RS= 120 kΩ
Page 10
January 1995 10
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
Fig.9 Test set-up for measuring forward transconductance gfs=dio/dviat vois constant (see also graph Fig.10).
Fig.10 Typical forward transconductance gfsas a function of the supply voltage at T
amb
=25°C.
A: average,
B: average + 2 s,
C: average − 2 s, in which: ‘s’ is the observed standard deviation.
Page 11
January 1995 11
Philips Semiconductors Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
Fig.11 Voltage gain VO/VIas a function of supply
voltage.
Fig.12 Supply current as a function of supply
voltage.
Fig.13 Test set-up for measuring graphs of Figs 11 and 12.
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