Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4517B
LSI
Dual 64-bit static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Dual 64-bit static shift register
DESCRIPTION
The HEF4517B consists of two identical, independent
64-bit static shift registers. Each register has separate
clock (CP), data input (D), parallel
input-enable/output-enable (PE/EO) and four 3-state
outputs of the 16th, 32nd, 48th and 64th bit positions
(O16to O64). Data at the D input is entered into the first bit
on the LOW to HIGH transition of the clock, regardless of
the state of PE/EO.
HEF4517B
LSI
When PE/
device is in the 64-bit serial mode.
When PE/EO is HIGH the outputs are disabled (high
impedance OFF-state), the 64-bit shift register is divided
into four 16-bit shift registers with D, O16, O32and O48as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
EO is LOW the outputs are enabled and the
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category LSI
DD
Page 3
Philips Semiconductors Product specification
Dual 64-bit static shift register
HEF4517B
LSI
Fig.2 Pinning diagram.
HEF4517BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4517BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4517BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
PINNING
CP
, CP
A
PE/
EOA, PE/EO
D
, D
A
B
, O
O
16A
O
, O
16B
, O
O
64A
B
32A
32B
64B
, O
, O
B
48A
48B
clock inputs
parallel input-enable/output-enable inputs
data inputs
3-state outputs/inputs
3-state outputs/inputs
3-state outputs
January 1995 3
Page 4
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January 1995 4
Philips Semiconductors Product specification
Dual 64-bit static shift register
Fig.3 Logic diagram (one shift register).
HEF4517B
LSI
Page 5
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January 1995 5
FUNCTION TABLE
INPUTS INPUTS/OUTPUTS
CP D PE/
data entered
into 1st bit
data entered
into 1st bit
X L no change no change no change no change no change
X H Z Z Z Z no change
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance state
= positive-going transition
= negative-going transition
EO O
L content of
16th bit
displayed
H data at
O
into 17th bit
entered
16
16
O
32
content of
32nd bit
displayed
data at
O32entered into
33rd bit
O
48
content of
48th bit
displayed
data at
O48entered
into 49th bit
O
content of
64th bit
displayed
remains in
‘Z’ state
64
MODE
One 64-bit shift
register. The content of the
shift register is
shifted over one stage
Four 16-bit shift
register. The content of
the shift registers is
shifted over one stage.
Philips Semiconductors Product specification
Dual 64-bit static shift register
HEF4517B
LSI
Page 6
Philips Semiconductors Product specification
Dual 64-bit static shift register
HEF4517B
AC CHARACTERISTICS
V
= 0 V; T
SS
Dynamic power 5 7 000 f
dissipation per 10 28 000 f
package (P) 15 70 000 f
AC CHARACTERISTICS
= 0 V; T
V
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition
times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; input transition times ≤ 20 ns
amb
V
DD
V
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
SYMBOL MIN. TYP. MAX.
5 220 440 ns 193 ns + (0,55 ns/pF) C
PHL
TYPICAL FORMULA FOR P (µW)
15 60 120 ns 52 ns + (0,16 ns/pF) C
5 190 380 ns 163 ns + (0,55 ns/pF) C
PLH
15 50 100 ns 42 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
= load capacitance (pF)
C
L
∑ (f
) = sum of outputs
oCL
V
= supply voltage (V)
DD
TYPICAL EXTRAPOLATION
FORMULA
85 170 ns 74 ns + (0,23 ns/pF) C
75 150 ns 64 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
LSI
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 6
Page 7
Philips Semiconductors Product specification
Dual 64-bit static shift register
AC CHARACTERISTICS
V
= 0 V; T
SS
Minimum clock 5 95 190 ns
pulse width; LOW 10 t
Set-up times 5 30 10 ns
O
, D → CP 10 t
n
Hold time 5 45 15 ns
O
, D → CP 10 t
n
3-state propagation
delays
Output disable times
PE/
EO → O
HIGH 10 t
LOW 10 t
Output enable times
PE/
EO → O
HIGH 10 t
LOW 10 t
Maximum clock 5 2 5 MHz
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
SYMBOL MIN. TYP. MAX.
WCPL
15 30 60 ns
su
25 5 ns
15 20 5 ns
hold
30 10 ns
15 25 10 ns
n
54080ns
PHZ
15 25 50 ns
5 50 100 ns
PLZ
15 25 50 ns
n
54590ns
PZH
15 20 40 ns
5 60 120 ns
PZL
15 25 50 ns
max
6 12 MHz
15 8 16 MHz
40 80 ns
30 60 ns
30 60 ns
25 50 ns
30 60 ns
HEF4517B
LSI
see also waveforms
Fig.4.
January 1995 7
Page 8
Philips Semiconductors Product specification
Dual 64-bit static shift register
HEF4517B
LSI
Fig.4 Waveforms showing minimum clock pulse width, set-up and hold times for On(as data input) and D to CP.
January 1995 8
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