Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4104B
MSI
Quadruple low to high voltage
translator with 3-state outputs
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
Quadruple low to high voltage translator
with 3-state outputs
HEF4104B
MSI
DESCRIPTION
The HEF4104B quadruple low voltage to high voltage
translator with 3-state outputs provides the capability of
interfacing low voltage circuits to high voltage circuits,
such as low voltage LOCMOS and TTL to high voltage
LOCMOS. It has four data inputs (I0to I3), an active HIGH
output enable input (EO), four data outputs (O0to O3) and
their complements (O0to O3).
With EO HIGH, O0to O3and O0to O3are in the low
impedance ON-state, either HIGH or LOW as determined
by I
0
to I3; with EO LOW, O0to O3and O0to O3are in the
high impedance OFF-state.
The device uses a common negative supply (V
SS
) and
separate positive supplies for inputs (V
DDI
) and outputs
(V
DD0
). V
DDI
must always be less than or equal to V
DDO
,
even during power turn-on and turn-off. For the
permissible operating range of V
DDI
and V
DDO
see graph
Fig.4.
Each input protection circuit is terminated between
V
DDO
and VSS. This allows the input signals to be driven
from any potential between V
DDO
and VSS, without regard
to current limiting. When driving from potentials greater
than V
DDO
or less than VSS, the current at each input must
be limited to 10 mA.
Fig.1 Functional diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4104BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4104BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4104BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
I
0
to I
3
data inputs
EO output enable input
O
0
to O
3
data outputs
O0to O
3
complementary data outputs
Fig.2 Pinning diagram.
Page 3
January 1995 3
Philips Semiconductors Product specification
Quadruple low to high voltage translator
with 3-state outputs
HEF4104B
MSI
Fig.3 Logic diagram.
Page 4
January 1995 4
Philips Semiconductors Product specification
Quadruple low to high voltage translator
with 3-state outputs
HEF4104B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
V
DD
V
SYMBOL TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In→ On, O
n
5 170 340 ns 143 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
80 160 ns 69 ns + (0,23 ns/pF) C
L
15 65 135 ns 57 ns + (0,16 ns/pF) C
L
5 170 340 ns 143 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
80 160 ns 69 ns + (0,23 ns/pF) C
L
15 70 140 ns 62 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
3-state propagation
delays
Output disable times
EO → O
n
, O
n
5 70 135 ns
HIGH 10 t
PHZ
55 110 ns
15 60 120 ns
5 70 135 ns
LOW 10 t
PLZ
55 105 ns
15 55 110 ns
Output enable times
EO → O
n
, O
n
5 195 395 ns
HIGH 10 t
PZH
95 195 ns
15 80 165 ns
5 195 395 ns
LOW 10 t
PZL
95 190 ns
15 80 160 ns
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 3 000 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 12 200 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 31 000 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load capacitance (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
Page 5
January 1995 5
Philips Semiconductors Product specification
Quadruple low to high voltage translator
with 3-state outputs
HEF4104B
MSI
Fig.4 V
DDO
as a function of V
DDI
; the shaded area shows the permissible operating range.
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