Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4085B
gates
Dual 2-wide 2-input AND-OR-invert
gate
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Dual 2-wide 2-input AND-OR-invert gate
DESCRIPTION
The HEF4085B is a dual 2-wide 2-input AND-OR-invert
gate, each with an additional input (A4or B4) which can be
used as either an expander input or an inhibit input. A
HIGH on A4or B4forces the output (OAor OB) LOW
independent of the other inputs (A0to A3or B0to B3). The
outputs OAand OBare fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
HEF4085B
gates
Fig.2 Pinning diagram.
HEF4085BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4085BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4085BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
January 1995 2
LOGIC FUNCTION
O
A0A1A2A3A4+⋅+⋅=
A
O
B0B1B2B3B4+⋅+⋅=
B
FAMILY DATA,
LIMITS category GATES
I
DD
See Family Specifications
Page 3
Philips Semiconductors Product specification
Dual 2-wide 2-input AND-OR-invert gate
HEF4085B
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
An,Bn→O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤20 ns
amb
V
DD
V
n
5 75 155 ns 48 ns + (0,55 ns/pF) C
SYMBOL TYP. MAX.
PHL
15 20 40 ns 12 ns + (0,16 ns/pF) C
5 65 135 ns 38 ns + (0,55 ns/pF) C
PLH
15 20 40 ns 12 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
TYPICAL EXTRAPOLATION
FORMULA
30 60 ns 19 ns + (0,23 ns/pF) C
30 55 ns 19 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
gates
L
L
L
L
L
L
L
L
L
L
L
L
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 750 f
dissipation per 10 3200 f
package (P) 15 9200 f
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
) = sum of outputs
∑ (f
oCL
V
= supply voltage (V)
DD
January 1995 3
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