Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4082B
gates
Dual 4-input AND gate
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Dual 4-input AND gate
DESCRIPTION
The HEF4082B provides the positive dual 4-input AND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.1 Functional diagram.
HEF4082B
gates
Fig.2 Pinning diagram.
HEF4082BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4082BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4082BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDDLIMITS category GATES
See Family Specifications
January 1995 2
Page 3
Philips Semiconductors Product specification
Dual 4-input AND gate
AC CHARACTERISTICS
V
=0V; T
SS
Propagation delays 5
In→ O
Output transition times 5
HIGH to LOW 10 30 60 ns 9 ns + (0,42 ns/pF) C
LOW to HIGH 10 t
Dynamic power 5 1500 f
dissipation per 10 6700 f
package (P) 15 16 800 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
10 30 60 ns 19 ns + (0,23 ns/pF) C
SYMBOL TYP. MAX.
t
PHL;tPLH
15 25 45 ns 17 ns + (0,16 ns/pF) C
t
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
V
DD
V
TYPICAL FORMULA FOR P (µW)
TYPICAL EXTRAPOLATION
FORMULA
65 125 ns 38 ns + (0,55 ns/pF) C
60 120 ns 10 ns + (1,0 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
where
2
fi= input freq. (MHz)
2
fo= output freq. (MHz)
C
= load capacitance (pF)
L
∑ (f
oCL
V
= supply voltage (V)
DD
) = sum of outputs
HEF4082B
gates
L
L
L
L
L
L
L
L
L
January 1995 3
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