Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4072B
gates
Dual 4-input OR gate
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Dual 4-input OR gate
DESCRIPTION
The HEF4072B provides the positive dual 4-input OR
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.1 Functional diagram.
HEF4072B
gates
Fig.2 Pinning diagram.
HEF4072BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4072BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4072BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995 2
Page 3
Philips Semiconductors Product specification
Dual 4-input OR gate
HEF4072B
gates
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
In→ O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤20 ns
amb
V
DD
V
n
5 80 155 ns 53 ns + (0,55 ns/pF) C
SYMBOL TYP. MAX.
PHL
15 25 55 ns 17 ns + (0,16 ns/pF) C
5 75 145 ns 48 ns + (0,55 ns/pF) C
PLH
15 25 55 ns 17 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
TYPICAL EXTRAPOLA TION
FORMULA
35 70 ns 24 ns + (0,23 ns/pF) C
35 70 ns 24 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
L
L
L
L
L
L
L
L
L
L
L
L
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 950 f
dissipation per 10 4500 f
package (P) 15 13 700 f
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
) = sum of outputs
∑ (f
oCL
V
= supply voltage (V)
DD
January 1995 3
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