Datasheet HEF4069UBU, HEF4069UBT, HEF4069UBPB, HEF4069UBP, HEF4069UBDB Datasheet (Philips)

DATA SH EET

Product specification
File under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF4069UB
gates

Hex inverter

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

January 1995 2

Philips Semiconductors Product specification

Hex inverter

HEF4069UB

gates

DESCRIPTION

The HEF4069UB is a general purpose hex inverter. Each
of the six inverters is a single stage.

Fig.1 Functional diagram.

HEF4069UBP(N): 14-lead DIL; plastic

(SOT27-1)

HEF4069UBD(F): 14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4069UBT(D): 14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

Fig.2 Pinning diagram.

Fig.3 Schematic diagram (one inverter).

FAMILY DATA, IDDLIMITS category GATES

See Family Specifications for V

IH/VIL

unbuffered stages

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Philips Semiconductors Product specification

Hex inverter

HEF4069UB

gates

AC CHARACTERISTICS

V

SS

= 0 V; T

amb

=25°C; CL= 50 pF; input transition times ≤ 20 ns

V

DD

V

SYMBOL TYP. MAX.

TYPICAL EXTRAPOLATION FORMULA

Propagation delays 5 45 90 ns 18 ns + (0,55 ns/pF) C

L

In→ O

n

10 t

PHL

20 40 ns 9 ns + (0,23 ns/pF) C

L

HIGH to LOW 15 15 25 ns 7 ns + (0,16 ns/pF) C

L

54080ns13ns+(0,55 ns/pF) C

L

LOW to HIGH 10 t

PLH

20 40 ns 9 ns + (0,23 ns/pF) C

L

15 15 30 ns 7 ns + (0,16 ns/pF) C

L

Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C

L

HIGH to LOW 10 t

THL

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

5 60 120 ns 10 ns + (1,0 ns/pF) C

L

LOW to HIGH 10 t

TLH

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

V

DD

V

TYPICAL FORMULA FOR P (µW)

Dynamic power 5 600 f

i

+∑(foCL) × V

DD

2

where

dissipation per 10 4 000 f

i

+∑(foCL) × V

DD

2

fi= input freq. (MHz)

package (P) 15 22 000 f

i

+∑(foCL) × V

DD

2

fo= output freq. (MHz)
C

L

= load capacitance (pF)

∑ (f

oCL

) = sum of outputs

V

DD

= supply voltage (V)

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Philips Semiconductors Product specification

Hex inverter

HEF4069UB

gates

Fig.4 Typical transfer characteristics;

___ VO;

___ID(drain current);

IO= 0; VDD= 5 V.

Fig.5 Typical transfer characteristics;

___ VO;

___ID(drain current);

IO= 0; VDD= 10 V.

Fig.6 Typical transfer characteristics;

___ VO;
___ID(drain current);
IO= 0; VDD= 15 V.

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Philips Semiconductors Product specification

Hex inverter

HEF4069UB

gates

APPLICATION INFORMATION

Some examples of applications for the HEF4069UB are shown below.
In Fig.7 an astable relaxation oscillator is given. The oscillation frequency is mainly determined by R1C1, provided

R1 << R2 and R2C2 << R1C1.

Fig.7 (a) Astable relaxation oscillator using two HEF4069UB inverters; the diodes may be BAW62; C2 is a

parasitic capacitance. (b) Waveforms at the points marked A, B, C and D in the circuit diagram.

The function of R2 is to minimize the influence of the forward voltage across
the protection diodes on the frequency; C2 is a stray (parasitic) capacitance.
The period T

p

is given by Tp=T1+T2, in which

V

ST

is the signal threshold level of the inverter. The period is fairly independent

of V

DD

, VST and temperature. The duty factor, however, is influenced by VST.

T

1

R1C1 In

V

DDVST

+

V

ST

---------------------------- -

and T

2

R1C1 In

2V

DDVST

–

V

DDVST

–

--------------------------------- -

where==

(a)

(b)

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Philips Semiconductors Product specification

Hex inverter

HEF4069UB

gates

Fig.8 Crystal oscillator for frequencies up to 10 MHz, using two HEF4069UB inverters.

(1) This inverter is added to amplify the

oscillator output voltage to a level
sufficient to drive other LOCMOS circuits.

Fig.9 Voltage gain (VO/VI) as a function of supply

voltage.

Fig.10 Supply current as a function of supply voltage.

Fig.11 Test set-up for measuring graphs of Figs 9

and 10.

It is also an example of an analogue
amplifier using one HEF4069UB.

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Philips Semiconductors Product specification

Hex inverter

HEF4069UB

gates

Fig.12 Test set-up for measuring forward transconductance gfs=dio/dviat vois constant (see also graph

Fig.13).

Fig.13 Typical forward transconductance gfsas a function of the supply voltage at T

amb

=25°C.

A : average,
B : average + 2 s,
C : average −2 s, where:

‘s’ is the observed standard
deviation.