Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4066B
gates
Quadruple bilateral switches
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to VDDa low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to VSSthe switch is
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram. Fig.2 Pinning diagram.
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
PINNING
APPLICATION INFORMATION
An example of application for the HEF4066B is:
• Analogue and digital switching
E
0
to E
3
enable inputs
Y
0
to Y
3
input/output terminals
Z
0
to Z
3
input/output terminals
Fig.3 Schematic diagram (one switch).
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January 1995 3
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
DC CHARACTERISTICS
T
amb
=25°C
Power dissipation per switch P max. 100 mW
For other RATINGS see Family Specifications
V
DD
V
SYMBOL MIN. TYP. MAX. CONDITIONS
ON resistance
5
R
ON
− 350 2500 Ω Enat V
DD
10 − 80 245 Ω Vis=VSSto V
DD
15 − 60 175 Ω see Fig.4
ON resistance
5
R
ON
− 115 340 Ω Enat V
DD
10 − 50 160 Ω Vis=V
SS
15 − 40 115 Ω see Fig.4
ON resistance
5
R
ON
− 120 365 Ω Enat V
DD
10 − 65 200 Ω Vis=V
DD
15 − 50 155 Ω see Fig.4
‘∆’ ON resistance 5
∆R
ON
− 25 −Ω Enat V
DD
between any two 10 − 10 −Ω Vis=VSSto V
DD
channels 15 − 5 −Ω see Fig.4
OFF state leakage 5
I
OZ
−−−nA
E
n
at V
SS
current, any 10 −−−nA
channel OFF 15 −−200 nA
E
n
input voltage 5
V
IL
− 2,25 1 V
I
is
=10µA
see Fig.9
LOW 10 − 4,50 2 V
15 − 6,75 2 V
V
DD
V
SYMBOL T
amb
(°c) CONDITIONS
−40 +25 +85
MAX. MAX. MAX.
Quiescent device 5
I
DD
1,0 1,0 7,5 µAV
SS
= 0; all valid
current 10 2,0 2,0 15,0 µA input combinations;
15 4,0 4,0 30,0 µAV
I=VSS
or V
DD
Input leakage current at E
n
15 ± I
IN
− 300 1000 nA Enat VSSor V
DD
Page 4
January 1995 4
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
NOTE
To avoid drawing VDDcurrent out of terminal Z, when switch current flows into terminals Y, the voltage drop across the
bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDDcurrent will flow out of
terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not
exceed VDDor VSS.
Fig.4 Test set-up for measuring RON.
Fig.5 Typical RONas a function of input voltage.
Enat V
DD
Iis= 200 µA
VSS=0V
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January 1995 5
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
AC CHARACTERISTICS
(1),(2)
VSS=0V; T
amb
=25°C; input transition times ≤ 20 ns
V
DD
V
SYMBOL TYP. MAX.
Propagation delays
V
is
→ V
os
51020ns
note 3HIGH to LOW 10 t
PHL
510ns
15 5 10 ns
51020ns
note 3LOW to HIGH 10 t
PLH
510ns
15 5 10 ns
Output disable times
E
n
→ V
os
5 80 160 ns
note 4HIGH 10 t
PHZ
65 130 ns
15 60 120 ns
5 80 160 ns
note 4LOW 10 t
PLZ
70 140 ns
15 70 140 ns
Output enable times
E
n
→ V
os
54080ns
note 4HIGH 10 t
PZH
20 40 ns
15 15 30 ns
54590ns
note 4LOW 10 t
PZL
20 40 ns
15 15 30 ns
Distortion, sine-wave 5 0,25 %
note 5response 10 0,04 %
15 0,04 %
Crosstalk between 5 − MHz
note 6any two channels 10 1 MHz
15 − MHz
Crosstalk; enable 5 − mV
note 7input to output 10 50 mV
15 − mV
OFF-state 5 − MHz
note 8feed-through 10 1 MHz
15 − MHz
ON-state frequency 5 − MHz
note 9response 10 90 MHz
15 − MHz
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January 1995 6
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
Notes
1. V
is
is the input voltage at a Y or Z terminal, whichever is assigned as input.
2. Vosis the output voltage at a Y or Z terminal, whichever is assigned as output.
3. RL=10kΩto VSS; CL= 50 pF to VSS; En=VDD;Vis=VDD(square-wave); see Figs 6 and 10.
4. RL=10kΩ;CL= 50 pF to VSS; En=VDD (square-wave);
Vis=VDDand RLto VSSfor t
PHZ
and t
PZH
;
Vis=VSSand RLto VDDfor t
PLZ
and t
PZL
; see Figs 6 and 11.
5. RL=10kΩ; CL= 15 pF; En=VDD; Vis=1⁄2V
DD(p-p)
(sine-wave, symmetrical about1⁄2VDD); fis= 1 kHz; see Fig.7.
6. RL=1kΩ; Vis=1⁄2V
DD(p-p)
(sine-wave, symmetrical about1⁄2VDD);
7. R
L
=10kΩto VSS; CL= 15 pF to VSS; En=VDD(square-wave); crosstalk is Vos (peak value); see Fig.6.
8. RL=1kΩ; CL= 5 pF; En=VSS; Vis=1⁄2V
DD(p-p)
(sine-wave, symmetrical about1⁄2VDD);
9. RL=1kΩ; CL= 5 pF; En=VDD; Vis=1⁄2V
DD(p-p)
(sine-wave, symmetrical about1⁄2VDD);
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 800 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 3 500 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 10 100 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load capacitance (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
20 log
V
os
(B)
V
is
A()
------------------ -
-50 dB; E
n
(A) VSSE;nB() VDD; see Fig. 8.===
20 log
V
os
V
is
-------- -
-50 dB; see Fig. 7.=
20 log
V
os
V
is
-------- -
-3 dB; see Fig. 7.=
Fig.6 Fig.7
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January 1995 7
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
Fig.8
Fig.9
Page 8
January 1995 8
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
Fig.10 Waveforms showing propagation delays from Visto Vos.
Fig.11 Waveforms showing output disable and enable times.
(1) Visat V
DD
(2) Visat VSS.
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