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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4066B
gates
Quadruple bilateral switches
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Quadruple bilateral switches
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to VDDa low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to VSSthe switch is
HEF4066B
gates
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram. Fig.2 Pinning diagram.
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
PINNING
to E
E
0
Y
to Y
0
to Z
Z
0
APPLICATION INFORMATION
An example of application for the HEF4066B is:
• Analogue and digital switching
enable inputs
3
input/output terminals
3
input/output terminals
3
Fig.3 Schematic diagram (one switch).
January 1995 2
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Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch P max. 100 mW
For other RATINGS see Family Specifications
DC CHARACTERISTICS
=25°C
T
amb
V
DD
V
5
ON resistance
10 − 80 245 Ω Vis=VSSto V
15 − 60 175 Ω see Fig.4
5
ON resistance
10 − 50 160 Ω Vis=V
15 − 40 115 Ω see Fig.4
5
ON resistance
10 − 65 200 Ω Vis=V
15 − 50 155 Ω see Fig.4
‘∆’ ON resistance 5
between any two 10 − 10 −Ω Vis=VSSto V
channels 15 − 5 −Ω see Fig.4
OFF state leakage 5
current, any 10 −−−nA
channel OFF 15 −−200 nA
E
input voltage 5
n
LOW 10 − 4,50 2 V
15 − 6,75 2 V
SYMBOL MIN. TYP. MAX. CONDITIONS
R
R
R
∆R
− 350 2500 Ω Enat V
ON
− 115 340 Ω Enat V
ON
− 120 365 Ω Enat V
ON
− 25 −Ω Enat V
ON
DD
DD
DD
SS
DD
DD
DD
DD
−−−nA
I
OZ
E
at V
n
SS
− 2,25 1 V
=10µA
I
V
IL
is
see Fig.9
gates
V
DD
V
SYMBOL T
−40 +25 +85
(°c) CONDITIONS
amb
MAX. MAX. MAX.
Quiescent device 5
current 10 2,0 2,0 15,0 µA input combinations;
I
DD
15 4,0 4,0 30,0 µAV
Input leakage current at E
n
15 ± I
IN
1,0 1,0 7,5 µAV
= 0; all valid
SS
I=VSS
or V
− 300 1000 nA Enat VSSor V
January 1995 3
DD
DD
Page 4
Philips Semiconductors Product specification
Quadruple bilateral switches
Fig.4 Test set-up for measuring RON.
HEF4066B
gates
Enat V
DD
Iis= 200 µA
VSS=0V
Fig.5 Typical RONas a function of input voltage.
NOTE
To avoid drawing VDDcurrent out of terminal Z, when switch current flows into terminals Y, the voltage drop across the
bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDDcurrent will flow out of
terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not
exceed VDDor VSS.
January 1995 4
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Philips Semiconductors Product specification
Quadruple bilateral switches
AC CHARACTERISTICS
VSS=0V; T
=25°C; input transition times ≤ 20 ns
amb
Propagation delays
V
→ V
is
os
Output disable times
E
→ V
n
os
Output enable times
E
→ V
n
os
Distortion, sine-wave 5 0,25 %
Crosstalk between 5 − MHz
Crosstalk; enable 5 − mV
OFF-state 5 − MHz
ON-state frequency 5 − MHz
(1),(2)
V
DD
V
SYMBOL TYP. MAX.
51020ns
PHL
510ns
15 5 10 ns
51020ns
PLH
510ns
15 5 10 ns
5 80 160 ns
PHZ
65 130 ns
15 60 120 ns
5 80 160 ns
PLZ
70 140 ns
15 70 140 ns
54080ns
PZH
20 40 ns
15 15 30 ns
54590ns
PZL
20 40 ns
15 15 30 ns
15 0,04 %
15 − MHz
15 − mV
15 − MHz
15 − MHz
HEF4066B
gates
note 3HIGH to LOW 10 t
note 3LOW to HIGH 10 t
note 4HIGH 10 t
note 4LOW 10 t
note 4HIGH 10 t
note 4LOW 10 t
note 5response 10 0,04 %
note 6any two channels 10 1 MHz
note 7input to output 10 50 mV
note 8feed-through 10 1 MHz
note 9response 10 90 MHz
January 1995 5
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Philips Semiconductors Product specification
Quadruple bilateral switches
V
DD
V
Dynamic power 5 800 f
dissipation per 10 3 500 f
package (P) 15 10 100 f
Notes
1. V
is the input voltage at a Y or Z terminal, whichever is assigned as input.
is
2. Vosis the output voltage at a Y or Z terminal, whichever is assigned as output.
3. RL=10kΩto VSS; CL= 50 pF to VSS; En=VDD;Vis=VDD(square-wave); see Figs 6 and 10.
4. RL=10kΩ;CL= 50 pF to VSS; En=VDD (square-wave);
Vis=VDDand RLto VSSfor t
Vis=VSSand RLto VDDfor t
PHZ
PLZ
5. RL=10kΩ; CL= 15 pF; En=VDD; Vis=1⁄2V
6. RL=1kΩ; Vis=1⁄2V
(B)
V
os
------------------ -
20 log
V
is
A()
-50 dB; E
(sine-wave, symmetrical about1⁄2VDD);
DD(p-p)
(A) VSSE;nB() VDD; see Fig. 8.===
n
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
and t
and t
;
PZH
; see Figs 6 and 11.
PZL
(sine-wave, symmetrical about1⁄2VDD); fis= 1 kHz; see Fig.7.
DD(p-p)
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
∑ (f
) = sum of outputs
oCL
= supply voltage (V)
V
DD
HEF4066B
gates
7. R
=10kΩto VSS; CL= 15 pF to VSS; En=VDD(square-wave); crosstalk is Vos (peak value); see Fig.6.
L
8. RL=1kΩ; CL= 5 pF; En=VSS; Vis=1⁄2V
V
os
-------- -
20 log
-50 dB; see Fig. 7.=
V
is
9. RL=1kΩ; CL= 5 pF; En=VDD; Vis=1⁄2V
V
os
-------- -
20 log
-3 dB; see Fig. 7.=
V
is
Fig.6 Fig.7
(sine-wave, symmetrical about1⁄2VDD);
DD(p-p)
(sine-wave, symmetrical about1⁄2VDD);
DD(p-p)
January 1995 6
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Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
Fig.8
Fig.9
January 1995 7
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Philips Semiconductors Product specification
Quadruple bilateral switches
Fig.10 Waveforms showing propagation delays from Visto Vos.
HEF4066B
gates
(1) Visat V
(2) Visat VSS.
January 1995 8
DD
Fig.11 Waveforms showing output disable and enable times.
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