Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4046B
MSI
Phase-locked loop
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
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January 1995 2
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
DESCRIPTION
The HEF4046B is a phase-locked loop circuit that consists
of a linear voltage controlled oscillator (VCO) and two
different phase comparators with a common signal input
amplifier and a common comparator input. A 7 V regulator
(zener) diode is provided for supply voltage regulation if
necessary. For functional description see further on in this
data.
Fig.1 Functional diagram.
HEF4046BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4046BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4046BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA
See Family Specifications
I
DD
LIMITS category MSI
See further on in this data.
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January 1995 3
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Fig.2 Pinning diagram.
PINNING
1. Phase comparator pulse output
2. Phase comparator 1 output
3. Comparator input
4. VCO output
5. Inhibit input
6. Capacitor C1 connection A
7. Capacitor C1 connection B
8. V
SS
9. VCO input
10. Source-follower output
11. Resistor R1 connection
12. Resistor R2 connection
13. Phase comparator 2 output
14. Signal input
15. Zener diode input for regulated supply.
FUNCTIONAL DESCRIPTION
VCO part
The VCO requires one external capacitor (C1) and one or
two external resistors (R1 or R1 and R2). Resistor R1 and
capacitor C1 determine the frequency range of the VCO.
Resistor R2 enables the VCO to have a frequency off-set
if required. The high input impedance of the VCO simplifies
the design of low-pass filters; it permits the designer a wide
choice of resistor/capacitor ranges. In order not to load the
low-pass filter, a source-follower output of the VCO input
voltage is provided at pin 10. If this pin (SF
OUT
) is used, a
load resistor (RSF) should be connected from this pin to
VSS; if unused, this pin should be left open. The VCO
output (pin 4) can either be connected directly to the
comparator input (pin 3) or via a frequency divider. A LOW
level at the inhibit input (pin 5) enables the VCO and the
source follower, while a HIGH level turns off both to
minimize stand-by power consumption.
Phase comparators
The phase-comparator signal input (pin 14) can be
direct-coupled, provided the signal swing is between the
standard HE4000B family input logic levels. The signal
must be capacitively coupled to the self-biasing amplifier
at the signal input in case of smaller swings. Phase
comparator 1 is an EXCLUSIVE-OR network. The signal
and comparator input frequencies must have a 50% duty
factor to obtain the maximum lock range. The average
output voltage of the phase comparator is equal to
1
⁄2V
DD
when there is no signal or noise at the signal input. The
average voltage to the VCO input is supplied by the
low-pass filter connected to the output of phase
comparator 1. This also causes the VCO to oscillate at the
centre frequency (fo). The frequency capture range (2 fc) is
defined as the frequency range of input signals on which
the PLL will lock if it was initially out of lock. The frequency
lock range (2 fL) is defined as the frequency range of input
signals on which the loop will stay locked if it was initially
in lock. The capture range is smaller or equal to the lock
range.
With phase comparator 1, the range of frequencies over
which the PLL can acquire lock (capture range) depends
on the low-pass filter characteristics and this range can be
made as large as the lock range. Phase comparator 1
enables the PLL system to remain in lock in spite of high
amounts of noise in the input signal. A typical behaviour of
this type of phase comparator is that it may lock onto input
frequencies that are close to harmonics of the VCO centre
frequency. Another typical behaviour is, that the phase
angle between the signal and comparator input varies
between 0° and 180° and is 90° at the centre frequency.
Figure 3 shows the typical phase-to-output response
characteristic.
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January 1995 4
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Figure 4 shows the typical waveforms for a PLL employing
phase comparator 1 in locked condition of fo.
Fig.3 Signal-to-comparator inputs phase
difference for comparator 1.
(1) Average output voltage.
Fig.4 Typical waveforms for phase-locked loop employing phase comparator 1 in locked condition of fo.
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January 1995 5
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Phase comparator 2 is an edge-controlled digital memory
network. It consists of four flip-flops, control gating and a
3-state output circuit comprising p and n-type drivers
having a common output node. When the p-type or n-type
drivers are ON, they pull the output up to VDDor down to
VSSrespectively. This type of phase comparator only acts
on the positive-going edges of the signals at SIGNINand
COMPIN. Therefore, the duty factors of these signals are
not of importance.
If the signal input frequency is higher than the comparator
input frequency, the p-type output driver is maintained ON
most of the time, and both the n and p-type drivers are
OFF (3-state) the remainder of the time. If the signal input
frequency is lower than the comparator input frequency,
the n-type output driver is maintained ON most of the time,
and both the n and p-type drivers are OFF the remainder
of the time. If the signal input and comparator input
frequencies are equal, but the signal input lags the
comparator input in phase, the n-type output driver is
maintained ON for a time corresponding to the phase
difference. If the comparator input lags the signal input in
phase, the p-type output driver is maintained ON for a time
corresponding to the phase difference. Subsequently, the
voltage at the capacitor of the low-pass filter connected to
this phase comparator is adjusted until the signal and
comparator inputs are equal in both phase and frequency.
At this stable point, both p and n-type drivers remain OFF
and thus the phase comparator output becomes an open
circuit and keeps the voltage at the capacitor of the
low-pass filter constant.
Moreover, the signal at the phase comparator pulse output
(PCP
OUT
) is a HIGH level which can be used for indicating
a locked condition. Thus, for phase comparator 2 no phase
difference exists between the signal and comparator
inputs over the full VCO frequency range. Moreover, the
power dissipation due to the low-pass filter is reduced
when this type of phase comparator is used because both
p and n-type output drivers are OFF for most of the signal
input cycle. It should be noted that the PLL lock range for
this type of phase comparator is equal to the capture
range, independent of the low-pass filter. With no signal
present at the signal input, the VCO is adjusted to its
lowest frequency for phase comparator 2 . Figure 5 shows
typical waveforms for a PLL employing this type of phase
comparator in locked condition.
Fig.5 Typical waveforms for phase-locked loop employing phase comparator 2 in locked condition.
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January 1995 6
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Figure 6 shows the state diagram for phase comparator 2.
Each circle represents a state of the comparator. The
number at the top, inside each circle, represents the state
of the comparator, while the logic state of the signal and
comparator inputs are represented by a ‘0’ for a logic LOW
or a ‘1’ for a logic HIGH, and they are shown in the left and
right bottom of each circle.
The transitions from one to another result from either a
logic change at the signal input (S) or the comparator input
(C). A positive-going and a negative-going transition are
shown by an arrow pointing up or down respectively.
The state diagram assumes, that only one transition on
either the signal input or comparator input occurs at any
instant. States 3, 5, 9 and 11 represent the condition at the
output when the p-type driver is ON, while states 2, 4, 10
and 12 determine the condition when the n-type driver is
ON. States 1, 6, 7 and 8 represent the condition when the
output is in its high impedance OFF state; i.e. both p and
n-type drivers are OFF, and the PCP
OUT
output is HIGH.
The condition at output PCP
OUT
for all other states is LOW.
Fig.6 State diagram for comparator 2.
S ↑: 0 to 1 transition at the signal input.
C ↓ : 1 to 0 transition at the comparator input.
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Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
DC CHARACTERISTICS
V
SS
=0V
Notes
1. Pin 15 open; pin 5 at V
DD
; pins 3 and 9 at VSS; pin 14 open.
2. Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 at VDD; input current pin 14 not included.
AC CHARACTERISTICS
V
SS
=0V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
V
DD
V
SYMBOL
T
amb
(°C)
−40 + 25 + 85
TYP. MAX. TYP. MAX. TYP. MAX.
Supply current 5 −− 20 −−− µA
(note 1) 10 I
D
−−300 −−− µA
15 −−750 −−− µA
Quiescent device 5 − 20 − 20 − 150 µA
current (note 2) 10 I
DD
− 40 − 40 − 300 µA
15 − 80 − 80 − 600 µA
V
DD
V
SYMBOL MIN. TYP. MAX.
Phase comparators
Operating supply voltage V
DD
315V
Input resistance 5 750 kΩ
at self-bias
operating point
at SIGN
IN
10 R
IN
220 kΩ
15 140 kΩ
A.C. coupled input 5 150 mV peak-to-peak values;
R1 = 10 kΩ; R2 = ∞;
C1 = 100 pF; independent
of the lock range
sensitivity 10 V
IN
150 mV
at SIGN
IN
15 200 mV
D.C. coupled input sensitivity
at SIGNIN; COMP
IN
5 1,5 V
full temperature range
LOW level 10 V
IL
3,0 V
15 4,0 V
5 3,5 V
HIGH level 10 V
IH
7,0 V
15 11,0 V
Input current 5 7 µA
SIGN
IN
at V
DD
at SIGN
IN
10 + I
IN
30 µA
15 70 µA
53µA
SIGN
IN
at V
SS
10 −I
IN
18 µA
15 45 µA
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January 1995 8
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Notes
1. Over the recommended component range.
VCO
Operating supply V
DD
3 15 V as fixed oscillator only
voltage 5 15 V phase-locked loop operation
Power dissipation 5 150 µW
f
o
= 10 kHz; R1 = 1 MΩ;
R2 = ∞; VCOINat1⁄2VDD;
see also Figs 10 and 11
10 P 2500 µW
15 9000 µW
Maximum operating 5 0,5 1,0 MHz
VCO
IN
at VDD;
R1 = 10 kΩ; R2 = ∞;
C1 = 50 pF
frequency 10 f
max
1,0 2,0 MHz
15 1,3 2,7 MHz
Temperature/ 5 0,220,30 %/°C
no frequency offset
(f
min
= 0);
see also note 1
frequency 10 0,040,05 %/°C
stability 15 0,010,05 %/°C
500,22 %/°C
with frequency offset
(f
min
> 0);
see also note 1
10 00,04 %/°C
15 00,01 %/°C
Linearity 5 0,50 % R1 > 10 kΩ see Fig.13
10 0,25 % R1 > 400 kΩ and Figs 14
15 0,25 % R1 = 1 MΩ 15 and 16
Duty factor at 5 50 %
VCO
OUT
10 δ 50 %
15 50 %
Input resistance at 5 10
6
MΩ
VCO
IN
10 R
IN
10
6
MΩ
15 10
6
MΩ
Source follower
Offset voltage 5 1,7 V
R
SF
=10kΩ;
VCOINat1⁄2V
DD
VCOINminus 10 2,0 V
SF
OUT
15 2,1 V
5 1,5 V
RSF=50kΩ;
VCOINat1⁄2V
DD
10 1,7 V
15 1,8 V
Linearity 5 0,3 %
R
SF
>50kΩ;
see Fig.13
10 1,0 %
15 1,3 %
Zener diode
Zener voltage V
Z
7,3 V IZ=50µA
Dynamic resistance R
Z
25 Ω IZ=1mA
V
DD
V
SYMBOL MIN. TYP. MAX.
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January 1995 9
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
DESIGN INFORMATION
VCO component selection
Recommended range for R1 and R2: 10 kΩ to 1 MΩ; for C1: 50 pF to any practical value.
1. VCO without frequency offset (R2 = ∞).
a) Given f
o
: use fo with Fig.7 to determine R1 and C1.
b) Given f
max
: calculate fofrom fo=1⁄2f
max
; use fowith Fig.7 to determine R1 and C1.
2. VCO with frequency offset.
a) Given foand fL: calculate f
min
from the equation f
min=fo−fL
; use f
min
with Fig.8 to determine R2 and C1; calculate
b) Given f
min
and f
max
: use f
min
with Fig.8 to determine R2 and C1; calculate
with Fig.9 to determine R2/R1 to obtain R1.
CHARACTERISTIC USING PHASE COMPARATOR 1 USING PHASE COMPARATOR 2
No signal on SIGN
IN
VCO in PLL system adjusts
to centre frequency (fo)
VCO in PLL system adjusts to min.
frequency (f
min
)
Phase angle between
SIGN
IN
and COMP
IN
90° at centre frequency (fo),
approaching 0° and 180° at
ends of lock range (2 fL)
always 0° in lock
(positive-going edges)
Locks on harmonics of
centre frequency
yes no
Signal input noise
rejection
high low
Lock frequency
range (2 f
L
)
the frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2 fL= full VCO frequency range = f
max
− f
min
Capture frequency
range (2 fC)
the frequency range of the input signal on which the loop will lock if it was initially
out of lock
depends on low-pass
filter characteristics; f
C
< f
L
fC= f
L
Centre frequency (fo) the frequency of the VCO when VCOINat1⁄2V
DD
f
max
f
min
---------- -
from the equation
f
max
f
min
---------- -
f
ofL
+
f
ofL
–
-------------- -
; use
f
max
f
min
---------- -
with Fig. 9 to determine the ratio R2/R1 to obtain R1.=
f
max
f
min
---------- -
; use
f
max
f
min
---------- -
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January 1995 10
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Fig.7 Typical centre frequency as a function of capacitor C1; T
amb
=25°C; VCOINat1⁄2VDD; INH at VSS; R2= ∞.
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January 1995 11
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Fig.8 Typical frequency offset as a function of capacitor C1; T
amb
=25°C; VCOINat VSS; INH at V
SS;
R1 = ∞.
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January 1995 12
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Fig.9 Typical ratio of R2/R1 as a function of the ratio f
max/fmin
.
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January 1995 13
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Fig.10 Power dissipation as a function of R1;
R2 = ∞; VCOINat1⁄2VDD; CL= 50 pF.
Fig.11 Power dissipation as a function of R2;
R1 = ∞; VCOINat VSS (0 V);
CL=50pF.
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Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Fig.12 Power dissipation of source follower as a
function of RSF; VCOINat1⁄2VDD; R1 = ∞ ;
R2 = ∞ .
Fig.13 Definition of linearity (see AC characteristics).
For VCO linearity:
Figure 13 and the above
formula also apply to
source follower linearity:
substitute V
SF OUT
for f.
∆V = 0,3 V at V
DD
=5V
∆V = 2,5 V at V
DD
=10V
∆V = 5 V at V
DD
=15V
f
′
o
f1f2+
2
-------------- -=
lin.
f
′
o
fo–
f
′
o
--------------- -
100%×=
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January 1995 15
Philips Semiconductors Product specification
Phase-locked loop
HEF4046B
MSI
Fig.14 VCO frequency linearity as a function of R1;
R2 = ∞;VDD=5V.
Fig.15 VCO frequency linearity as a function of R1;
R2 = ∞;VDD=10V.
Fig.16 VCO frequency linearity as a function of R1;
R2 = ∞;VDD=15V.
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