Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4035B
MSI
4-bit universal shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
4-bit universal shift register
DESCRIPTION
The HEF4035B is a fully synchronous edge-triggered 4-bit
shift register with a clock input (CP), four synchronous
parallel data inputs (P0to P3), two synchronous serial data
inputs (J, K), a synchronous parallel enable input (PE),
buffered parallel outputs from all 4-bit positions (O0 to O3),
a true/complement input (T/C) and an overriding
asynchronous master reset input (MR). Each register is of
a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is
edge-triggered on the LOW to HIGH transition of the CP
input. When PE is HIGH, data is loaded into the register
from P
to P3 on the LOW to HIGH transition of CP.
0
HEF4035B
MSI
When PE is LOW, data is shifted into the first register
position from J and
shifted one position to the right on the LOW to HIGH
transition of CP. D-type entry is obtained by
interconnecting J andK. When J = HIGH and K = LOW the
first stage is in the toggle mode. When J = LOW and
K = HIGH the first stage is in the hold mode.
The outputs (O0 to O3) are either inverting or non-inverting,
depending on T/C state. With T/C HIGH, O0 to O3 are
non-inverting (active HIGH) and when T/C is LOW, O0 to
O3 are inverting (active LOW).
A HIGH on MR resets all four bit positions (O0to
O3= LOW if T/C = HIGH, O0to O3= HIGH if T/C = LOW)
independent of all other input conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
K and all the data in the register is
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category MSI
DD
Page 3
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January 1995 3
Philips Semiconductors Product specification
4-bit universal shift register
Fig.2 Logic diagram.
HEF4035B
MSI
Page 4
Philips Semiconductors Product specification
4-bit universal shift register
Fig.3 Pinning diagram.
PINNING
PE parallel enable input
P
to P3parallel data inputs
0
J first stage J-input (active HIGH)
K first stage K-input (active LOW)
CP clock input (LOW to HIGH edge-triggered)
T/
C true/complement input
MR master reset input
O
to O3buffered parallel outputs
0
HEF4035B
MSI
HEF4035BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4035BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4035BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FUNCTION TABLES
Serial operation first stage
INPUTS OUTPUT
CP J
KMR O
0 + 1
H H L H D flip-flop
L L L L D flip-flop
HLL
LHL O
O0toggle
0
X X X H L reset
Note
1. T/C = HIGH; PE = LOW
MODE OF
OPERATION
no change
Parallel operation
INPUTS OUTPUTS
CP
P
P1P2P3O0O1O
0
HHHHH H H H
LLLLL L L L
Notes
C = HIGH; PE = HIGH; MR = LOW
1. T/
= positive-going transition
H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
O
2
3
January 1995 4
Page 5
Philips Semiconductors Product specification
4-bit universal shift register
HEF4035B
AC CHARACTERISTICS
V
=0V; T
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
MR → O
HIGH to LOW 10 t
LOW to HIGH 10 t
T/C → O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
5 170 340 ns 143 ns + (0,55 ns/pF) C
SYMBOL MIN. TYP. MAX.
PHL
15 50 100 ns 42 ns + (0,16 ns/pF) C
5 150 300 ns 123 ns + (0,55 ns/pF) C
PLH
15 50 100 ns 42 ns + (0,16 ns/pF) C
n
5 115 230 ns 88 ns + (0,55 ns/pF) C
PHL
15 40 80 ns 32 ns + (0,16 ns/pF) C
5 115 230 ns 88 ns + (0,55 ns/pF) C
PLH
15 40 80 ns 32 ns + (0,16 ns/pF) C
n
5 105 210 ns 78 ns + (0,55 ns/pF) C
PHL
15 35 70 ns 27 ns + (0,16 ns/pF) C
5 85 170 ns 58 ns + (0,55 ns/pF) C
PLH
15 35 70 ns 27 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
TYPICAL EXTRAPOLATION
FORMULA
70 140 ns 59 ns + (0,23 ns/pF) C
65 130 ns 54 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
45 90 ns 34 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 5
Page 6
Philips Semiconductors Product specification
4-bit universal shift register
V
DD
V
Minimum clock 5 80 40 ns
pulse width; LOW 10 t
15 30 15 ns
Minimum MR 5 50 25 ns
pulse width; HIGH 10 t
15 20 10 ns
Recovery time 5 50 20 ns
for MR 10 t
15 25 10 ns
Set-up times 5 40 5 ns
P
→ CP 10 t
n
15 15 0 ns
55025ns
PE → CP 10 t
15 30 10 ns
55540ns
J,
K → CP 10 t
15 25 10 ns
Hold times 5 25 10 ns
P
→ CP 10 t
n
15 20 10 ns
515−5ns
PE → CP 10 t
15 5 −5ns
510−5ns
J,
K → CP 10 t
15 10 0 ns
Maximum clock 5 5 10 MHz
pulse frequency 10 f
15 15 30 MHz
SYMBOL MIN. TYP. MAX.
WCPL
WMRH
RMR
su
su
su
hold
hold
hold
max
40 20 ns
30 15 ns
40 15 ns
25 0 ns
35 15 ns
35 15 ns
20 10 ns
10 −5ns
10 0 ns
12 25 MHz
HEF4035B
MSI
TYPICAL EXTRAPOLATION
FORMULA
see also waveforms Figs 4
and 5
V
DD
V
Dynamic power 5 1 000 f
dissipation per 10 6 000 f
package (P) 15 20 000 f
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
January 1995 6
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
= load cap. (pF)
C
L
∑ (f
) = sum of outputs
oCL
= supply voltage (V)
V
DD
Page 7
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January 1995 7
Philips Semiconductors Product specification
4-bit universal shift register
Fig.4 Waveforms showing minimum clock pulse width, set-up times, hold times. Set-up times and hold times are shown as positive values but
may be specified as negative values.
HEF4035B
MSI
Page 8
Philips Semiconductors Product specification
4-bit universal shift register
Fig.5 Waveforms showing minimum MR pulse width and MR recovery
time.
HEF4035B
MSI
APPLICATION INFORMATION
Some examples of applications for
the HEF4035B are:
• Counters, registers, arithmetic-unit
registers, shift-left/shift-right
registers.
• Serial-to-parallel/parallel-to-serial
conversions.
• Sequence generation.
• Control circuits.
• Code conversion.
Fig.6 Shift-left/shift-right register.
January 1995 8
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