Datasheet hef4031b DATASHEETS (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4031B MSI

64-stage static shift register

Product speciﬁcation File under Integrated Circuits, IC04

January 1995

Page 2

Philips Semiconductors Product speciﬁcation

64-stage static shift register

DESCRIPTION

The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL load.

Data from DA or DB, as determined by the state of A/B, is shifted into the first shift register position and all the data in

HEF4031B

MSI

the register is shifted one position to the right on the LOW to HIGH transition of CP. D by a HIGH on A/B. Registers can be cascaded either by connecting all CP inputs together or by driving CP of the most right-hand register with the system clock and connecting CO to CP of the preceding register. When the second technique is used in the recirculating mode, a flip-flop must be used to store O63 of the most right-hand register until the most left-hand register is clocked.

is selected by a LOW, and D

Fig.1 Functional diagram.

Fig.2 Pinning diagram.

HEF4031BP(N): 16-lead DIL; plastic (SOT38-1) HEF4031BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4031BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America

PINNING

, DBdata inputs

A/B data select input CP clock input (LOW to HIGH edge-triggered) CO buffered clock output O

FAMILY DATA, I

See Family Specifications

buffered output from the 64th stage complementary buffered output from the 64th

stage

LIMITS category MSI

January 1995 2

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Philips Semiconductors Product speciﬁcation

64-stage static shift register

HEF4031B

MSI

Fig.3 Logic diagram.

DC CHARACTERISTICS

= 0 V; VI=VSSor V

(°c)

amb

SYMBOL

−40 + 25 + 85

MIN. MAX. MIN. MAX. MIN. MAX.

Output (source) 5 4, 6 1,0 0,85 0,65 mA

current 10 9,5 −I HIGH; O HIGH; O

63 63

15 13,5 10,0 8,5 6,5 mA

5 2,5 −I

3,0 2,5 2,0 mA

Output (sink) 4,75 0,4 2,7 2,3 1,8 mA

current 10 0,5 I LOW; O

15 1,5 24,0 20,0 16,0 mA

9,5 8,0 6,3 mA

January 1995 3

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Philips Semiconductors Product speciﬁcation

64-stage static shift register

HEF4031B

MSI

AC CHARACTERISTICS

=0V; T

Propagation delays

CP → O

HIGH to LOW 10 t

LOW to HIGH 10 t

CP → O

HIGH to LOW 10 t

LOW to HIGH 10 t

CP → CO 5 70 140 ns 43 ns + (0,55 ns/pF) C

HIGH to LOW 10 t

LOW to HIGH 10 t

Output transition times; 5 25 50 ns 5 ns + (0,40 ns/pF) C

HIGH to LOW 15 8 16 ns 2 ns + (0,13 ns/pF) C

LOW to HIGH 10 t

Output transition times; O63, CO 5 60 120 ns 10 ns + (1,0 ns/pF) C

HIGH to LOW 10 t

LOW to HIGH 10 t

=25°C; CL= 50 pF; input transition times ≤ 20 ns

amb

SYMBOL MIN. TYP. MAX.

5 180 360 ns 167 ns + (0,26 ns/pF) C

PHL

15 45 90 ns 40 ns + (0,11 ns/pF) C

5 170 340 ns 148 ns + (0,45 ns/pF) C

PLH

15 45 90 ns 39 ns + (0,13 ns/pF) C

5 190 380 ns 163 ns + (0,55 ns/pF) C

PHL

15 50 100 ns 42 ns + (0,16 ns/pF) C

5 190 380 ns 163 ns + (0,55 ns/pF) C

PLH

15 50 100 ns 42 ns + (0,16 ns/pF) C

PHL

15 25 50 ns 17 ns + (0,16 ns/pF) C

5 55 110 ns 28 ns + (0,55 ns/pF) C

PLH

15 25 50 ns 17 ns + (0,16 ns/pF) C

10 t

THL

54080ns8ns+(0,65 ns/pF) C

TLH

15 13 26 ns 3 ns + (0,20 ns/pF) C

THL

15 20 40 ns 6 ns + (0,28 ns/pF) C

5 60 120 ns 10 ns + (1,0 ns/pF) C

TLH

15 20 40 ns 6 ns + (0,28 ns/pF) C

TYPICAL EXTRAPOLA TION

FORMULA

65 130 ns 57 ns + (0,16 ns/pF) C

65 130 ns 56 ns + (0,19 ns/pF) C

75 150 ns 64 ns + (0,23 ns/pF) C

35 70 ns 24 ns + (0,23 ns/pF) C

30 60 ns 19 ns + (0,23 ns/pF) C

12 24 ns 3 ns + (0,18 ns/pF) C

20 40 ns 5 ns + (0,30 ns/pF) C

30 60 ns 9 ns + (0,42 ns/pF) C

L L

L L L L L L L L L L L L L L L L L L L L L L L L L L L

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Philips Semiconductors Product speciﬁcation

64-stage static shift register

AC CHARACTERISTICS

=0V; T

Set-up times 5 25 0 ns

A,DB

A/B → CP 10 t

Hold times 5 40 10 ns

, DB→ CP 10 t

A/B → CP 10 t

Minimum clock

pulse width; 5 180 90 ns

LOW 10 t

Maximum clock 5 2,5 5 MHz

pulse frequency 10 f

=25°C; CL= 50 pF; input transition times ≤ 20 ns

amb

→CP 10 t

SYMBOL MIN. TYP. MAX.

15 10 −10 ns

53010ns

15 10 −5ns

hold

15 40 10 ns

54010ns

hold

15 40 10 ns

WCPL

15 50 25 ns

max

15 10 20 MHz

25 −5ns

15 0 ns

40 10 ns

70 35 ns

7 14 MHz

HEF4031B

MSI

TYPICAL EXTRAPOLATION

FORMULA

APPLICATION INFORMATION

An example of an application for the HEF4031B is:

• Serial shift register.

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January 1995 7

(1) Recirculating input. (2) Mode control: VDD= recirculation; ground (VSS) = new data.

Fig.5 Cascading using direct clocking for high speed operation (see clock rise and fall time requirements).

APPLICATION INFORMATION

Philips Semiconductors Product speciﬁcation

64-stage static shift register

(1) Recirculating input. (2) Mode control: VDD= recirculation; ground (VSS) = new data. (3) For recirculation mode only, FF to delay data until first register delayed clocking has occurred. (4) Delayed clock-to-clock; new data into first register.

Fig.6 Cascading using delayed clocking for reduced clock drive requirements.

HEF4031B

MSI