Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4024B
MSI
7-stage binary counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
7-stage binary counter
HEF4024B
MSI
DESCRIPTION
The HEF4024B is a 7-stage binary ripple counter with a
clock input (CP), and overriding asynchronous master
reset input (MR) and seven fully buffered parallel outputs
(O0to O6). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of CP. Each
counter stage is a static toggle flip-flop.
Fig.1 Functional diagram.
HEF4024BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4024BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4024BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
APPLICATION INFORMATION
Some examples of applications for the HEF4024B are:
• Frequency dividers
• Time delay circuits
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
CP clock input (HIGH to LOW triggered)
MR master reset input
O
0
to O
6
buffered parallel outputs
Page 3
January 1995 3
Philips Semiconductors Product specification
7-stage binary counter
HEF4024B
MSI
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Fig.3 Logic diagram.
Page 4
January 1995 4
Philips Semiconductors Product specification
7-stage binary counter
HEF4024B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
V
DD
V SYMBOL MIN. TYP. MAX.
TYPICAL
EXTRAPOLATION
FORMULA
Propagation delays
CP → O
0
5 100 200 ns 73 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
40 75 ns 29 ns + (0,23 ns/pF) C
L
15 25 50 ns 17 ns + (0,16 ns/pF) C
L
5 105 210 ns 78 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
45 85 ns 34 ns + (0,23 ns/pF) C
L
15 30 60 ns 22 ns + (0,16 ns/pF) C
L
On→ On+ 1 5 60 120 ns 33 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
25 50 ns 14 ns + (0,23 ns/pF) C
L
15 20 40 ns 12 ns + (0,16 ns/pF) C
L
5 50 100 ns 23 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
20 40 ns 9 ns + (0,23 ns/pF) C
L
15 15 30 ns 7 ns + (0,16 ns/pF) C
L
MR → O
n
5 120 240 ns 93 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
45 90 ns 34 ns + (0,23 ns/pF) C
L
15 30 60 ns 22 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
Minimum clock 5 60 30 ns
pulse width; HIGH 10 t
WCPH
30 15 ns
15 20 10 ns
Minimum MR 5 80 40 ns
pulse width; HIGH 10 t
WMRH
35 20 ns
15 25 15 ns
Recovery time 5 20 10 ns
for MR 10 t
RMR
15 5 ns
15 15 5 ns
Maximum clock 5 5 10 MHz
pulse frequency 10 f
max
13 25 MHz
15 18 35 MHz
Page 5
January 1995 5
Philips Semiconductors Product specification
7-stage binary counter
HEF4024B
MSI
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 500 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 2100 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 5200 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load cap. (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
Fig.4 Waveforms showing propagation delays for MR to Onand CP to O0, minimum MR andCP pulse widths
and recovery time for MR.
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