Datasheet HEF40240BU, HEF40240BT, HEF40240BPB, HEF40240BP, HEF40240BDB Datasheet (Philips)
...Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF40240B
buffers
Octal inverting buffers with 3-state
outputs
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
Octal inverting buffers with 3-state outputs
HEF40240B
buffers
DESCRIPTION
The HEF40240B is an octal inverting buffer with 3-state
outputs. It features output stages with high current output
capability suitable for driving highly capacitive loads.
The 3-state outputs are controlled by the output enable
inputsEOAandEOB. A HIGH onEO causes the outputs to
assume a high impedance OFF-state. The device also
features hysteresis on all inputs to improve noise
immunity.
Schmitt-trigger action in the inputs makes the circuit highly
tolerant to slower input rise and fall times.
The HEF40240B is pin and functionally compatible with
the TTL ‘240’ device.
Fig.1 Functional diagram.
PINNING
FAMILY DATA, IDDLIMITS category buffers
See Family Specifications
HEF40240BP(N): 20-lead DIL; plastic (SOT146-1)
HEF40240BD(F): 20-lead DIL; ceramic (cerdip) (SOT152)
HEF40240BT(D): 20-lead SO; plastic (SOT163-1)
( ): Package Designator North America
I
A1
to I
A4
inputs
I
B1
to I
B4
inputs
O
A1
to O
A4
bus outputs
O
B1
to O
B4
bus outputs
EOA, EO
B
output enable inputs (active LOW)
Fig.2 Pinning diagram.
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January 1995 3
Philips Semiconductors Product specification
Octal inverting buffers with 3-state outputs
HEF40240B
buffers
Fig.3 Logic diagram (one buffer).
TRUTH TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance off state
INPUTS OUTPUT
I
n
EO O
n
HL L
LL H
XH Z
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
See Family Specifications except for:
DC CHARACTERISTICS
V
SS
=0 V
D.C. current into any input ± I
I
max. 10 mA
D.C. source or sink current into any output ± I
O
max. 25 mA
D.C. current into the supply terminals ± I max. 100 mA
PARAMETER
V
DDVOHVOL
SYMBOL
T
amb
(°C)
UNIT−40 +25 +85
V V V MIN. TYP. MIN. TYP. MIN. TYP.
Output current 5 3,6 −−I
OH
9,3 − 10,0 24,0 10,7 − mA
HIGH 10 8,4 −−I
OH
14,4 − 15,0 46,0 15,0 − mA
15 13,2 −−I
OH
19,5 − 20,0 62,0 19,8 − mA
Output current 5 4,6 −−I
OH
0,75 − 0,6 1,2 0,45 mA
HIGH 10 9,5 −−I
OH
1,85 − 1,5 3,0 1,1 − mA
15 13,5 −−I
OH
14,5 − 15,0 50,0 15,5 − mA
Output current 5 − 0,4 I
OL
2,9 − 2,3 5,4 1,75 − mA
LOW 10 − 0,5 I
OL
9,5 − 7,6 17,0 5,50 − mA
15 − 1,5 I
OL
30,0 − 25,0 45,0 19,0 − mA
Hysteresis 5 −−V
H
−−−220,0 −− mV
voltage 10 −−V
H
−−−250,0 −− mV
(any input) 15 −−V
H
−−−320,0 −− mV
Page 4
January 1995 4
Philips Semiconductors Product specification
Octal inverting buffers with 3-state outputs
HEF40240B
buffers
Fig.4 Typical output source current characteristic.
(1) P-channel MOS transistor conducting.
(2) P-channel MOS transistor and bipolar
n-p-n transistor conducting.
Fig.5 Schematic diagram of output stage.
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; input transition times ≤ 20 ns
ALL BUFFERS SWITCHING
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 4 250 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 17 000 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 46 000 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load capacitance (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
Page 5
January 1995 5
Philips Semiconductors Product specification
Octal inverting buffers with 3-state outputs
HEF40240B
buffers
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
PARAMETER
V
DD
V
SYMBOL MIN. TYP. MAX. UNIT
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
I
An/Bn
→ O
An/Bn
5 95 190 ns 83 ns + (0,24 ns/pF) C
L
HIGH to LOW 10 t
PHL
40 80 ns 35 ns + (0,10 ns/pF) C
L
15 30 60 ns 26 ns + (0,07 ns/pF) C
L
I
An/Bn
→ O
An/Bn
5 85 170 ns 82 ns + (0,06 ns/pF) C
L
LOW to HIGH 10 t
PLH
40 80 ns 38 ns + (0,03 ns/pF) C
L
15 30 60 ns 29 ns + (0,02 ns/pF) C
L
Output transition 5 40 80 ns
see Fig.6
times 10 t
THL
20 40 ns
HIGH to LOW 15 15 30 ns
53060ns
LOW to HIGH 10 t
TLH
20 40 ns
15 15 30 ns
3-state propagation delays
Output disable times
EO → O
An/Bn
5 70 140 ns
HIGH 10 t
PHZ
35 70 ns
15 30 60 ns
5 75 150 ns
LOW 10 t
PLZ
40 80 ns
15 30 60 ns
Output enable times
EO → O
An/Bn
5 80 160 ns
HIGH 10 t
PZH
35 70 ns
15 30 60 ns
5 90 180 ns
LOW 10 t
PZL
40 80 ns
15 30 60 ns
Page 6
January 1995 6
Philips Semiconductors Product specification
Octal inverting buffers with 3-state outputs
HEF40240B
buffers
Fig.6 Output transition times as a function of the load capacitance.
t
TLH
− − − − t
THL
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