Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4020B
MSI
14-stage binary counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
14-stage binary counter
HEF4020B
MSI
DESCRIPTION
The HEF4020B is a 14-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O0, O3 to
O13). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of the state of
CP. Each counter stage is a static toggle flip-flop. A feature
of the HEF4020B is: high speed (typ. 35 MHz at
VDD= 15 V).
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, IDDLIMITS category MSI
See Family Specifications
HEF4020BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4020BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4020BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
CP clock input (HIGH to LOW edge
triggered)
MR master reset input (active HIGH)
O
0
, O3 to O
13
parallel outputs
Page 3
January 1995 3
Philips Semiconductors Product specification
14-stage binary counter
HEF4020B
MSI
Fig.3 Logic diagram.
Page 4
January 1995 4
Philips Semiconductors Product specification
14-stage binary counter
HEF4020B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
V
DD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLA TION
FORMULA
Propagation delays
CP →Ο
0
5 105 210 ns 78 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
45 90 ns 34 ns + (0,23 ns/pF) C
L
15 30 65 ns 22 ns + (0,16 ns/pF) C
L
5 105 210 ns 78 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
50 95 ns 39 ns + (0,23 ns/pF) C
L
15 35 70 ns 27 ns + (0,16 ns/pF) C
L
On→ On+ 1 5 80 160 ns 53 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
30 60 ns 19 ns + (0,23 ns/pF) C
L
15 20 40 ns 12 ns + (0,16 ns/pF) C
L
5 70 140 ns 43 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
25 50 ns 14 ns + (0,23 ns/pF) C
L
15 20 40 ns 12 ns + (0,16 ns/pF) C
L
MR → O
n
5 180 360 ns 153 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
90 180 ns 79 ns + (0,23 ns/pF) C
L
15 70 140 ns 62 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
Minimum clock 5 50 25 ns
pulse width; HIGH 10 t
WCPH
25 15 ns
15 20 10 ns
Minimum MR 5 130 65 ns
pulse width; HIGH 10 t
WMRH
95 50 ns
15 90 45 ns
Recovery time 5 115 60 ns
for MR 10 t
RMR
65 35 ns
15 55 25 ns
Maximum clock 5 5 10 MHz
pulse frequency 10 f
max
13 25 MHz
15 18 35 MHz
Page 5
January 1995 5
Philips Semiconductors Product specification
14-stage binary counter
HEF4020B
MSI
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 600 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 2 800 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 8 200 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load cap. (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths.
Page 6
January 1995 6
Philips Semiconductors Product specification
14-stage binary counter
HEF4020B
MSI
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Fig.5 Timing diagram.
Loading...