Datasheet HEF40195BT, HEF40195BPB, HEF40195BDB, HEC40195BDB Datasheet (Philips)

DATA SH EET

Product specification
File under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF40195B
MSI

4-bit universal shift register

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

January 1995 2

Philips Semiconductors Product specification

4-bit universal shift register

HEF40195B

MSI

DESCRIPTION

The HEF40195B is a fully synchronous edge-triggered
4-bit shift register with a clock input (CP), four synchronous
parallel data inputs (P0to P3), two synchronous serial data
inputs (J, K), a synchronous parallel enable input (PE),
buffered parallel outputs from all 4-bit positions (O0to O3),
a buffered inverted output from the last bit position (O3)
and an overriding asynchronous master reset input (MR).
Each register stage is of a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is
edge-triggered on the LOW to HIGH transition of the CP

input. When

PE is LOW, data are loaded into the register
from P0to P3on the LOW to HIGH transition of CP. When
PE is HIGH, data are shifted into the first register position
from J and K and all the data in the register are shifted one
position to the right on the LOW to HIGH transition of CP.
D-type entry is obtained by interconnecting J and K.
When J is HIGH and K is LOW, the first stage is in the
toggle mode. When J is LOW andK is HIGH, the first stage
is in the hold mode.
A LOW on MR resets all four bit positions (O0to
O3= LOW, O3= HIGH) independent of all other input
conditions.

Fig.1 Functional diagram.

Fig.2 Pinning diagram.

FAMILY DATA, IDDLIMITS category MSI

See Family Specifications

HEF40195BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF40195BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF40195BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

January 1995 3

Philips Semiconductors Product specification

4-bit universal shift register

HEF40195B

MSI

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Fig.3 Logic diagram.

January 1995 4

Philips Semiconductors Product specification

4-bit universal shift register

HEF40195B

MSI

PINNING

FUNCTION TABLE

Notes

1. H = HIGH state (the more positive voltage)

2. L = LOW state (the less positive voltage)

3. X = state is immaterial

4. t

n + 1

= state after next LOW to HIGH transition of CP

PE parallel enable input (active LOW)
P

0

to P

3

parallel data inputs
J first stage J-input (active HIGH)
K first stage K-input (active LOW)
CP clock input (LOW to HIGH edge triggered)
MR master reset input (active LOW)
O

0

to O

3

buffered parallel outputs
O

3

buffered inverted output from last stage

OPERATING MODE

INPUTS (

MR = HIGH) OUTPUTS AT t

n + 1

PE J KP

0

P

1

P

2

P

3

O

0

O

1

O

2

O

3

O

3

shift mode

HLLXXXXLO

0

O

1

O

2

O

2

HLHXXXXO

0

O

0

O

1

O

2

O

2

HHLXXXXO

0

O

0

O

1

O

2

O

2

HHHXXXXHO

0

O

1

O

2

O

2

parallel entry mode

LXXLLLLLLLLH
LXXHHHHHHHHL

January 1995 5

Philips Semiconductors Product specification

4-bit universal shift register

HEF40195B

MSI

AC CHARACTERISTICS

V

SS

= 0 V; T

amb

=25°C; CL= 50 pF; input transition times ≤ 20 ns

V

DD

V

SYMBOL MIN. TYP. MAX.

TYPICAL EXTRAPOLATION

FORMULA

Propagation delays

CP → O

n

5 105 215 ns 78 ns + (0,55 ns/pF) C

L

HIGH to LOW 10 t

PHL

50 95 ns 39 ns + (0,23 ns/pF) C

L

15 35 65 ns 27 ns + (0,16 ns/pF) C

L

5 90 180 ns 63 ns + (0,55 ns/pF) C

L

LOW to HIGH 10 t

PLH

45 85 ns 34 ns + (0,23 ns/pF) C

L

15 30 60 ns 22 ns + (0,16 ns/pF) C

L

CP → O

3

5 125 255 ns 98 ns + (0,55 ns/pF) C

L

HIGH to LOW 10 t

PHL

50 100 ns 39 ns + (0,23 ns/pF) C

L

15 35 70 ns 27 ns + (0,16 ns/pF) C

L

5 120 240 ns 93 ns + (0,55 ns/pF) C

L

LOW to HIGH 10 t

PLH

50 105 ns 39 ns + (0,23 ns/pF) C

L

15 35 75 ns 27 ns + (0,16 ns/pF) C

L

MR → O

n

5 100 205 ns 73 ns + (0,55 ns/pF) C

L

HIGH to LOW 10 t

PHL

45 90 ns 34 ns + (0,23 ns/pF) C

L

15 30 65 ns 22 ns + (0,16 ns/pF) C

L

5 125 235 ns 98 ns + (0,55 ns/pF) C

L

LOW to HIGH 10 t

PLH

55 115 ns 44 ns + (0,23 ns/pF) C

L

15 40 85 ns 32 ns + (0,16 ns/pF) C

L

Output transition

times 5 60 120 ns 10 ns + (1,0 ns/pF) C

L

HIGH to LOW 10 t

THL

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

5 60 120 ns 10 ns + (1,0 ns/pF) C

L

LOW to HIGH 10 t

TLH

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

January 1995 6

Philips Semiconductors Product specification

4-bit universal shift register

HEF40195B

MSI

AC CHARACTERISTICS

V

SS

= 0 V; T

amb

=25°C; CL= 50 pF; input transition times ≤ 20 ns

V

DD

V

SYMBOL MIN. TYP. MAX.

Set-up times 5 70 35 ns

see also waveforms
Figs 4 and 5

J, K → CP 10 t

su

20 10 ns

15 10 5 ns

58540ns

P

n

→CP 10 t

su

25 10 ns

15 10 5 ns

5 115 55 ns

PE → CP 10 t

su

45 20 ns

15 30 15 ns

Hold times 5 15 −20 ns

J,

K → CP 10 t

hold

5 −5ns

15 0 −5ns

520−25 ns

P

n

→ CP 10 t

hold

10 −5ns

15 0 −5ns

510−50 ns

PE → CP 10 t

hold

5 −20 ns

15 5 −10 ns

Minimum clock 5 60 30 ns

pulse width; LOW 10 t

WCPL

25 10 ns

15 20 10 ns

Minimum MR 5 100 50 ns

pulse width; HIGH 10 t

WMRL

40 20 ns

15 30 15 ns

Recovery time 5 30 10 ns

for

MR 10 t

RMR

15 5 ns

15 15 5 ns

Maximum clock 5 5 10 MHz

pulse frequency 10 f

max

14 28 MHz

15 19 39 MHz

January 1995 7

Philips Semiconductors Product specification

4-bit universal shift register

HEF40195B

MSI

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V

DD

V

TYPICAL FORMULA FOR P (µW)

Dynamic power 5 1900 f

i

+∑(foCL) × V

DD

2

where

dissipation per 10 8300 f

i

+∑(foCL) × V

DD

2

fi= input freq. (MHz)

package (P) 15 22 800 f

i

+∑(foCL) × V

DD

2

fo= output freq. (MHz)
C

L

= load capacitance (pF)

∑ (f

oCL

) = sum of outputs

V

DD

= supply voltage (V)

Fig.4 Waveforms showing set-up times, hold times for J, K and Pninputs; minimum MR pulse width, MRto output delays and MR to CP

recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be specified
as negative values.

January 1995 8

Philips Semiconductors Product specification

4-bit universal shift register

HEF40195B

MSI

APPLICATION INFORMATION

Some examples of applications for the HEF40195B are:

• Serial data transfer

• Parallel data transfer

• Serial to parallel data transfer

• Parallel to serial data transfer

Fig.5 Waveforms showing set-up and hold times for PE input. Set-up and hold times are shown as positive

values but may be specified as negative values.