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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40194B
MSI
4-bit bidirectional universal shift
register
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
4-bit bidirectional universal shift register
DESCRIPTION
The HEF40194B is a 4-bit bidirectional shift register with
two mode control inputs (S0and S1), a clock input (CP), a
serial data shift left input (DSL), a serial data shift right input
(DSR), four parallel data inputs (P0to P3), an overriding
asynchronous master reset input (MR), and four buffered
parallel outputs (O0to O3). When LOW, MR resets all
stages and forces O0to O3 LOW, overriding all other input
conditions. When MR is HIGH, the operation mode is
controlled by S0and S1as shown in the function table.
HEF40194B
MSI
Serial and parallel operation are edge-triggered on the
LOW to HIGH transition of CP. The inputs at which the
data are to be entered and S
set-up time before the LOW to HIGH transition of CP.
, S1must be stable for a
0
Fig.1 Functional diagram.
PINNING
, S
S
0
1
to P
P
0
D
SR
D
SL
mode control inputs
parallel data inputs
3
serial data shift right input
serial data shift left input
CP clock input (LOW to HIGH edge-triggered)
MR master reset input (active LOW)
O
0
to O
buffered parallel outputs
3
Fig.2 Pinning diagram.
HEF40194BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40194BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40194BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, I
LIMITS category MSI
DD
See Family Specifications
January 1995 2
Page 3
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January 1995 3
Philips Semiconductors Product specification
4-bit bidirectional universal shift register
Fig.3 Logic diagram.
HEF40194B
MSI
Page 4
Philips Semiconductors Product specification
4-bit bidirectional universal shift register
FUNCTION TABLE
INPUTS (
OPERATING MODE S
1
S
0
D
hold L L X X X O
shift left
shift right
parallel load
HL X L X O
HL X H X O
LH L X X LO
LH H X X HO
HH X X L LLLL
H H X X H HHHH
Notes
1. H =HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. t
= state after next LOW to HIGH transition of CP
n + 1
MR = HIGH) OUTPUTS AT T
SR
D
SL
P0TO P
3
O
0
0
1
1
HEF40194B
MSI
n + 1
O
O
O
O
1
1
2
2
0
0
O
2
O
2
O
3
O
3
O
1
O
1
O
3
O
3
L
H
O
2
O
2
AC CHARACTERISTICS
V
SS
= 0 V; T
=25°C; input transition times ≤ 20 ns
amb
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 1 500 f
dissipation per 10 6 900 f
package (P) 15 18 900 f
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load cap. (pF)
L
∑ (f
) = sum of outputs
oCL
= supply voltage (V)
V
DD
January 1995 4
Page 5
Philips Semiconductors Product specification
4-bit bidirectional universal shift register
HEF40194B
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
MR → O
HIGH to LOW 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
SYMBOL MIN. TYP. MAX.
5 100 205 ns 73 ns + (0,55 ns/pF) C
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
5 80 165 ns 53 ns + (0,55 ns/pF) C
PLH
15 25 55 ns 17 ns + (0,16 ns/pF) C
n
5 85 175 ns 58 ns + (0,55 ns/pF) C
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
TYPICAL EXTRAPOLA TION
FORMULA
40 85 ns 29 ns + (0,23 ns/pF) C
35 70 ns 24 ns + (0,23 ns/pF) C
40 80 ns 29 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 5
Page 6
Philips Semiconductors Product specification
4-bit bidirectional universal shift register
V
DD
V
Set-up times 5 80 40 ns
, DSR, DSL→ CP 10 t
P
n
15 20 10 ns
S
→ CP 10 t
n
15 40 20 ns
Hold times 5 10 −30 ns
P
, DSR, DSL→ CP 10 t
n
15 5 −5ns
S
→ CP 10 t
n
15 10 −10 ns
Minimum clock 5 50 25 ns
pulse width; LOW 10 t
15 20 10 ns
Minimum
MR 5 80 40 ns
pulse width; LOW 10 t
15 30 15 ns
Recovery time 5 30 10 ns
for
MR 10 t
15 15 5 ns
Maximum clock 5 6 12 MHz
pulse frequency 10 f
15 20 40 MHz
SYMBOL MIN. TYP. MAX.
su
30 15 ns
5 140 70 ns
su
hold
60 30 ns
5 −10 ns
525−45 ns
hold
WCPL
WMRL
RMR
max
15 −15 ns
20 10 ns
40 20 ns
15 5 ns
15 30 MHz
HEF40194B
MSI
TYPICAL EXTRAPOLA TION
FORMULA
see also waveforms
Figs 4 and 5
January 1995 6
Page 7
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January 1995 7
Philips Semiconductors Product specification
4-bit bidirectional universal shift register
Fig.4 Waveforms showing set-up times, hold times for DSR,DSLand Pninputs; minimum MR pulse width, MR to output delays and MR to CP
recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be
specified as negative values.
HEF40194B
MSI
Page 8
Philips Semiconductors Product specification
4-bit bidirectional universal shift register
HEF40194B
MSI
Fig.5 Waveforms showing set-up times and hold times for S0and S1inputs. Set-up and hold times are shown
as positive values but may be specified as negative values.
APPLICATION INFORMATION
Some examples of applications for the HEF40194B are:
• Arithmetic unit register
• Serial/parallel converter.
January 1995 8
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