Datasheet HEF40174BU, HEF40174BT, HEF40174BPB, HEF40174BP, HEF40174BDB Datasheet (Philips)

DATA SH EET

Product specification
File under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF40174B
MSI

Hex D-type flip-flop

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

January 1995 2

Philips Semiconductors Product specification

Hex D-type flip-flop

HEF40174B

MSI

DESCRIPTION

The HEF40174B is a hex edge-triggered D-type flip-flop
with six data inputs (D0to D5), a clock input (CP), an
overriding asynchronous master reset input (MR), and six

buffered outputs (O

0

to O5). Information on D0to D5is
transferred to O0to O5on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O0to O5= LOW) independent of CP and D0to D5.

Fig.1 Functional diagram.

FAMILY DATA, IDDLIMITS category MSI

See Family Specifications

HEF40174BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF40174BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF40174BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

Fig.2 Pinning diagram.

PINNING

FUNCTION TABLE

Notes

1. H = HIGH state (the more positive voltage)

L = LOW state (the less positive voltage)
X = state is immaterial

= positive-going transition
= negative-going transition

D

0

to D5data inputs
CP clock input (LOW to HIGH; edge-triggered)
MR master reset input (active LOW)
O

0

to O5buffered outputs

INPUTS OUTPUT

CP D

MR O

HH H

LH L

X H no change

XXL L

January 1995 3

Philips Semiconductors Product specification

Hex D-type flip-flop

HEF40174B

MSI

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

Fig.3 Logic diagram.

January 1995 4

Philips Semiconductors Product specification

Hex D-type flip-flop

HEF40174B

MSI

AC CHARACTERISTICS

V

SS

= 0 V; T

amb

=25°C; CL= 50 pF; input transition times ≤ 20 ns

V

DD

V

SYMBOL MIN. TYP. MAX.

TYPICAL EXTRAPOLATION

FORMULA

Propagation delays

CP → O

n

5 75 155 ns 48 ns + (0,55 ns/pF) C

L

HIGH to LOW 10 t

PHL

30 65 ns 19 ns + (0,23 ns/pF) C

L

15 20 45 ns 12 ns + (0,16 ns/pF) C

L

5 75 155 ns 48 ns + (0,55 ns/pF) C

L

LOW to HIGH 10 t

PLH

30 65 ns 19 ns + (0,23 ns/pF) C

L

15 20 45 ns 12 ns + (0,16 ns/pF) C

L

MR → O

n

5 85 175 ns 58 ns + (0,55 ns/pF) C

L

HIGH to LOW 10 t

PHL

35 70 ns 24 ns + (0,23 ns/pF) C

L

15 25 50 ns 17 ns + (0,16 ns/pF) C

L

Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C

L

HIGH to LOW 10 t

THL

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

5 60 120 ns 10 ns + (1,0 ns/pF) C

L

LOW to HIGH 10 t

TLH

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

Set-up time 5 20 10 ns

see also waveforms
Fig.4

D

n

→ CP 10 t

su

10 5 ns

15 10 5 ns

Hold time 5 10 0 ns

D

n

→ CP 10 t

hold

50 ns

15 5 0 ns

Minimum clock 5 70 35 ns

pulse width; LOW 10 t

WCPL

30 15 ns

15 20 10 ns

Minimum MR pulse 5 70 35 ns

width; LOW 10 t

WMRL

35 15 ns

15 25 10 ns

Recovery time 5 45 25 ns

for

MR 10 t

RMR

20 10 ns

15 15 5 ns

Maximum clock 5 5 11 MHz

pulse frequency 10 f

max

15 30 MHz

15 20 45 MHz

January 1995 5

Philips Semiconductors Product specification

Hex D-type flip-flop

HEF40174B

MSI

APPLICATION INFORMATION

Some examples of applications for the HEF40174B are:

• Shift registers

• Buffer/storage register

• Pattern generator

V

DD

V

TYPICAL FORMULA FOR P(µW)

Dynamic power 5 3500 f

i

+∑(foCL) × V

DD

2

where

dissipation per 10 16 000 f

i

+∑(foCL) × V

DD

2

fi= input freq. (MHz)

package (P) 15 42 000 f

i

+∑(foCL) × V

DD

2

fo= output freq. (MHz)
C

L

= load capacitance (pF)

∑ (f

oCL

) = sum of outputs

V

DD

= supply voltage (V)

Fig.4 Waveforms showing minimum pulse widths for CP and MR, MR to CP recovery time, and set-up time and

hold time for Dnto CP. Set-up and hold times are shown as positive values but may be specified as
negative values.