Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40174B
MSI
Hex D-type flip-flop
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Hex D-type flip-flop
DESCRIPTION
The HEF40174B is a hex edge-triggered D-type flip-flop
with six data inputs (D0to D5), a clock input (CP), an
overriding asynchronous master reset input (MR), and six
HEF40174B
MSI
buffered outputs (O
transferred to O0to O5on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O0to O5= LOW) independent of CP and D0to D5.
to O5). Information on D0to D5is
0
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF40174BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40174BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40174BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDDLIMITS category MSI
See Family Specifications
January 1995 2
PINNING
D
to D5data inputs
0
CP clock input (LOW to HIGH; edge-triggered)
MR master reset input (active LOW)
O
to O5buffered outputs
0
FUNCTION TABLE
INPUTS OUTPUT
CP D
HH H
LH L
X H no change
XXL L
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
MR O
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January 1995 3
Philips Semiconductors Product specification
Hex D-type flip-flop
Fig.3 Logic diagram.
HEF40174B
MSI
Page 4
Philips Semiconductors Product specification
Hex D-type flip-flop
HEF40174B
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
MR → O
HIGH to LOW 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
Set-up time 5 20 10 ns
D
→ CP 10 t
n
Hold time 5 10 0 ns
D
→ CP 10 t
n
Minimum clock 5 70 35 ns
pulse width; LOW 10 t
Minimum MR pulse 5 70 35 ns
width; LOW 10 t
Recovery time 5 45 25 ns
for
MR 10 t
Maximum clock 5 5 11 MHz
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
5 75 155 ns 48 ns + (0,55 ns/pF) C
SYMBOL MIN. TYP. MAX.
PHL
15 20 45 ns 12 ns + (0,16 ns/pF) C
5 75 155 ns 48 ns + (0,55 ns/pF) C
PLH
15 20 45 ns 12 ns + (0,16 ns/pF) C
n
5 85 175 ns 58 ns + (0,55 ns/pF) C
PHL
15 25 50 ns 17 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
su
15 10 5 ns
hold
15 5 0 ns
WCPL
15 20 10 ns
WMRL
15 25 10 ns
RMR
15 15 5 ns
max
15 20 45 MHz
TYPICAL EXTRAPOLATION
30 65 ns 19 ns + (0,23 ns/pF) C
30 65 ns 19 ns + (0,23 ns/pF) C
35 70 ns 24 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
10 5 ns
50 ns
30 15 ns
see also waveforms
Fig.4
35 15 ns
20 10 ns
15 30 MHz
FORMULA
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 4
Page 5
Philips Semiconductors Product specification
Hex D-type flip-flop
V
DD
V
Dynamic power 5 3500 f
dissipation per 10 16 000 f
package (P) 15 42 000 f
TYPICAL FORMULA FOR P(µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
HEF40174B
MSI
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
∑ (f
) = sum of outputs
oCL
= supply voltage (V)
V
DD
Fig.4 Waveforms showing minimum pulse widths for CP and MR, MR to CP recovery time, and set-up time and
hold time for Dnto CP. Set-up and hold times are shown as positive values but may be specified as
negative values.
APPLICATION INFORMATION
Some examples of applications for the HEF40174B are:
• Shift registers
• Buffer/storage register
• Pattern generator
January 1995 5
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