Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4013B
flip-flops
Dual D-type flip-flop
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Dual D-type flip-flop
DESCRIPTION
The HEF4013B is a dual D-type flip-flop which features
independent set direct (SD), clear direct (CD), clock inputs
(CP) and outputs (O, O). Data is accepted when CP is
LOW and transferred to the output on the positive-going
edge of the clock. The active HIGH asynchronous
clear-direct (CD) and set-direct (SD) are independent and
override the D or CP inputs. The outputs are buffered for
best system performance. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
HEF4013B
flip-flops
FUNCTION TABLES
INPUTS OUTPUTS
S
HLXX H L
LHXX L H
HHXX H H
S
LL L L H
LL H H L
Notes
1. H = HIGH state (the more positive voltage)
C
D
CP D O O
D
INPUTS OUTPUTS
C
D
CP D On+ 1 On+ 1
D
L = LOW state (the less positive voltage)
X = state is immaterial
Fig.1 Functional diagram.
= positive-going transition
+ 1 = state after clock positive transition
O
n
PINNING
D data inputs
CP clock input (L to H edge-triggered)
S
asynchronous set-direct input (active HIGH)
D
C
asynchronous clear-direct input (active HIGH)
D
O true output
O complement output
HEF4013BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4013BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4013BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
January 1995 2
FAMILY DATA, I
LIMITS category FLIP-FLOPS
DD
See Family Specifications
Page 3
Philips Semiconductors Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
January 1995 3
Fig.3 Logic diagram (one flip-flop).
Page 4
Philips Semiconductors Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
AC CHARACTERISTICS
V
=0V; T
SS
Propagation delays
CP → O, O 5 110 220 ns 83 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
SD→ O 5 100 200 ns 73 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
SD→ O 5 75 150 ns 48 ns + (0,55 ns/pF) C
LOW to HIGH 10 t
CD→ O 5 100 200 ns 73 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
CD→ O 5 60 120 ns 33 ns + (0,55 ns/pF) C
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
SYMBOL MIN. TYP. MAX.
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
5 95 190 ns 68 ns + (0,55 ns/pF) C
PLH
15 30 60 ns 22 ns + (0,16 ns/pF) C
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
PLH
15 25 50 ns 17 ns + (0,16 ns/pF) C
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
PLH
15 20 40 ns 12 ns + (0,16 ns/pF) C
TYPICAL EXTRAPOLA TION
FORMULA
45 90 ns 34 ns + (0,23 ns/pF) C
40 80 ns 29 ns + (0,23 ns/pF) C
40 80 ns 29 ns + (0,23 ns/pF) C
35 70 ns 24 ns + (0,23 ns/pF) C
40 80 ns 29 ns + (0,23 ns/pF) C
30 60 ns 19 ns + (0,23 ns/pF) C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
15 20 40 ns 6 ns + (0,28 ns/pF) C
January 1995 4
L
L
L
L
L
L
Page 5
Philips Semiconductors Product specification
Dual D-type flip-flop
AC CHARACTERISTI CS
V
=0V; T
SS
Set-up time 5 40 20 ns
D → CP 10 t
Hold time 5 20 0 ns
D → CP 10 t
Minimum clock 5 60 30 ns
pulse width; LOW 10 t
Minimum S
width; HIGH 10 t
Minimum C
width; HIGH 10 t
Recovery time 5 15 −5ns
for S
D
Recovery time 5 40 25 ns
for C
D
Maximum clock 5 7 14 MHz
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
SYMBOL MIN. TYP. MAX.
su
25 10 ns
15 15 5 ns
hold
20 0 ns
15 15 0 ns
WCPL
30 15 ns
15 20 10 ns
pulse 5 50 25 ns
D
WSDH
24 12 ns
15 20 10 ns
pulse 5 50 25 ns
D
WCDH
24 12 ns
15 20 10 ns
10 t
RSD
15 0 ns
15 15 0 ns
10 t
RCD
25 10 ns
15 25 10 ns
max
14 28 MHz
15 20 40 MHz
HEF4013B
flip-flops
see also waveforms
Figs 4 and 5
V
DD
V
Dynamic power 5 850 f
dissipation per 10 3 600 f
package (P) 15 9 000 f
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
January 1995 5
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= total load cap. (pF)
L
∑ (f
) = sum of outputs
oCL
V
= supply voltage (V)
DD
Page 6
Philips Semiconductors Product specification
Dual D-type flip-flop
HEF4013B
flip-flops
Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.
January 1995 6
Page 7
Philips Semiconductors Product specification
Dual D-type flip-flop
APPLICATION INFORMATION
Some examples of applications for the HEF4013B are:
• Counters/dividers
• Registers
• Toggle flip-flops
Fig.6 Typical application of the HEF4013B in an n-stage shift register.
HEF4013B
flip-flops
Fig.7 Typical application of the HEF4013B in a binary ripple up-counter; divide-by-2n.
Fig.8 Typical application of the HEF4013B in a modified ring counter; divide-by-(n + 1).
January 1995 7
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