Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4012B
gates
Dual 4-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Dual 4-input NAND gate
DESCRIPTION
The HEF4012B provides the positive dual 4-input NAND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
HEF4012B
gates
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDDLIMITS category GATES
see Family Specifications
HEF4012BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4012BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4012BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
January 1995 2
Page 3
Philips Semiconductors Product specification
Dual 4-input NAND gate
HEF4012B
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
In→ O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤20 ns
amb
V
DD
V
n
5 70 135 ns 43 ns + (0,55 ns/pF) C
SYMBOL TYP MAX
PHL
15 20 35 ns 12 ns + (0,16 ns/pF) C
5 70 140 ns 43 ns + (0,55 ns/pF) C
PLH
15 25 50 ns 17 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
TYPICAL EXTRAPOLATION
FORMULA
25 50 ns 14 ns + (0,23 ns/pF) C
30 60 ns 19 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
gates
L
L
L
L
L
L
L
L
L
L
L
L
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 1100 f
dissipation per 10 4400 f
package (P) 15 12 900 f
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
) = sum of outputs
∑ (f
oCL
V
= supply voltage (V)
DD
January 1995 3
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