Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4011B
gates
Quadruple 2-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Quadruple 2-input NAND gate
DESCRIPTION
The HEF4011B provides the positive quadruple 2-input
NAND function. The outputs are fully buffered for highest
noise immunity and pattern insensitivity of output
impedance.
HEF4011B
gates
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDDLIMITS category GATES
See Family Specifications
HEF4011BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4011BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4011BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
January 1995 2
Page 3
Philips Semiconductors Product specification
Quadruple 2-input NAND gate
HEF4011B
gates
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays 5 55 110 ns 28 ns + (0,55 ns/pF) C
In→ O
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
Dynamic power 5 1300 f
dissipation per 10 6000 f
package (P) 15 20 100 f
=25°C; CL= 50 pF; input transition times ≤20 ns
amb
V
DD
V
n
10 t
SYMBOL TYP MAX
; t
PHL
PLH
15 20 35 ns 12 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
V
DD
V
TYPICAL FORMULA FOR P (µW)
TYPICAL EXTRAPOLATION
FORMULA
25 45 ns 14 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
∑ (f
) = sum of outputs
oCL
V
= supply voltage (V)
DD
L
L
L
L
L
L
L
L
L
January 1995 3
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