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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4006B
MSI
18-stage static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
18-stage static shift register
DESCRIPTION
The HEF4006B is an 18-stage shift register arranged as
two 4-stage and two 5-stage shift registers with a common
clock input (CP). The two 4-stage shift registers each have
a data input (DA, DB) and a data output (O3A, O3B); the two
HEF4006B
MSI
5-stage shift registers each have a data input (D
data outputs from the fourth and fifth stages (O3C, O4C,
O3D, O4D).
The registers can be operated in parallel or interconnected
to form a single shift register of up to 18 bits. Data are
shifted into the first register position of each register from
the data inputs (DA to DD) and all the data in each register
are shifted one position to the right on the HIGH to LOW
transition of CP.
, DD) and
C
Fig.1 Functional diagram.
FUNCTION TABLE
D
n
D
1
CP O
X no change
Notes
1. X = state is immaterial
2. = positive-going transition
Fig.2 Pinning diagram.
HEF4006BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4006BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4006BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
(5)
n
D
1
PINNING
D
A
to D
D
data inputs
CP clock input
(HIGH to LOW; edge-triggered)
to O3D; O4C; O4Ddata outputs
O
3A
FAMILY DATA, I
LIMITS category MSI
DD
See Family Specifications
3. = negative-going transition
4. D
= either HIGH or LOW
1
5. The moment D1 appears at O depends on the register
length.
January 1995 2
Page 3
Philips Semiconductors Product specification
18-stage static shift register
HEF4006B
MSI
Fig.3 Logic diagram.
January 1995 3
Page 4
Philips Semiconductors Product specification
18-stage static shift register
HEF4006B
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
Minimum clock 5 60 30 ns
pulse width; HIGH 10 t
Set-up time 5 20 10 ns
D
→ CP 10 t
n
Hold time 5 5 −5ns
D
→CP 10 t
n
Maximum clock 5 9 18 MHz
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤20 ns
amb
V
DD
V
n
5 90 180 ns 63 ns + (0,55 ns/pF) C
SYMBOL MIN TYP MAX
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
5 90 180 ns 63 ns + (0,55 ns/pF) C
PLH
15 35 70 ns 27 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
WCPH
40 20 ns
15 30 15 ns
su
10 5 ns
15 5 0 ns
hold
50 ns
15 5 0 ns
max
15 30 MHz
15 18 36 MHz
TYPICAL EXTRAPOLATION
FORMULA
40 80 ns 29 ns + (0,23 ns/pF) C
40 85 ns 29 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
see also waveforms Fig.4
MSI
L
L
L
L
L
L
L
L
L
L
L
L
V
DD
V
Dynamic power 5 600 f
dissipation per 10 3200 f
package (P) 15 11 600 f
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
January 1995 4
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
∑ (f
) = sum of outputs
oCL
= supply voltage (V)
V
DD
Page 5
Philips Semiconductors Product specification
18-stage static shift register
HEF4006B
MSI
Fig.4 Waveforms showing minimum clock pulse width, and set-up and hold-times for Dnto CP. Set-up and hold
times are shown as positive values but may be specified as negative values.
January 1995 5
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