Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4750V
LSI
Frequency synthesizer
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
Page 2
January 1995 2
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
DESCRIPTION
The HEF4750V frequency synthesizer is one of a pair of
LOCMOS devices, primarily intended for use in
high-performance frequency synthesizers, e.g. in all
communication, instrumentation, television and broadcast
applications. A combination of analogue and digital
techniques results in an integrated circuit that enables high
performance. The complementary device is the universal
divider type HEF4751V.
Together with a standard prescaler, the two LOCMOS
integrated circuits offer low-cost single loop synthesizers
with full professional performance. Salient features offered
(in combination with HEF4751V) are:
• Wide choice of reference frequency using a single
crystal.
• High-performance phase comparator low phase
noise low spurii.
• System operation to > 1 GHz.
• Typical 15 MHz input at 10 V.
• Flexible programming:
frequency offsets
ROM compatible
fractional channel capability.
• Programme range 6
1
⁄2 decades, including up to
3 decades of prescaler control.
• Division range extension by cascading.
• Built-in phase modulator.
• Fast lock feature.
• Out-of-lock indication.
• Low power dissipation and high noise immunity.
APPLICATION INFORMATION
Some examples of applications for the HEF4750V in
combination with the HEF4751V are:
• VHF/UHF mobile radios.
• HF s.s.b. transceivers.
• Airborne and marine communications and navaids.
• Broadcast transmitters.
• High quality radio and television receivers.
• High performance citizens band equipment.
• Signal generators.
SUPPLY VOLTAGE
RATING RECOMMENDED OPERATING
−0,5 to +15 9,5 to 10,5 V
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January 1995 3
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
HEF4750VD(F): 28-lead DIL; ceramic (cerdip)
(SOT135)
( ): Package Designator North America
Fig.1 Pinning diagram.
PINNING
R phase comparator input, reference
V phase comparator input
STB strobe input
TCA timing capacitor C
A
pin
TCB timing capacitor C
B
pin
TCC timing capacitor C
C
pin
TRA biasing pin (resistor R
A
)
PC
1
analogue phase comparator output
PC
2
digital phase comparator output
MOD phase modulation input
OL out-of-lock indication
OSC reference oscillator/buffer input
XTAL reference oscillator/buffer output
A
0
to A
9
programming inputs/programmable divider
NS
0
, NS1programming inputs, prescaler
OUT reference divider output
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January 1995 4
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
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Fig.2 Block diagram comprising five basic functions: phase comparator 1 (PC1), phase comparator 2 (PC2), phase modulator, reference
oscillator and reference divider. These functions are described separately.
N.B. PC1= analogue output; PC2= 3-state output.
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January 1995 5
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
FUNCTIONAL DESCRIPTION
Phase comparator 1
Phase comparator 1 (PC1) is built around a SAMPLE and
HOLD circuit. A negative-going transition at the V-input
causes the hold capacitor (C
A
) to be discharged and after
a specified delay, caused by the Phase Modulator by
means of an internal V’ pulse, it produces a positive-going
ramp. A negative-going transition at the R-input terminates
the ramp. Capacitor C
A
holds the voltage that the ramp
has attained. Via an internal sampling switch this voltage
is transferred to CCand in turn buffered and made
available at output PC1.
If the ramp terminates before an R-input is present, an
internal end of ramp (EOR) signal is produced.
These actions are illustrated in Fig.3.
The resultant phase characteristic is shown in Fig.4.
Fig.3 Waveforms associated with PC1.
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January 1995 6
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Fig.4 Phase characteristic of PC1.
PC1 is designed to have a high gain, typically 3200 V/cycle
(at 12,5 kHz). This enables a low noise performance.
Phase comparator 2
Phase comparator 2 (PC2) has a wide range, which
enables faster lock times to be achieved than otherwise
would be possible. It has a linear ± 360° phase range,
which corresponds to a gain of typically 5 V/cycle.
This digital phase comparator has three stable states:
• reset state,
• V’ leads R state,
• R leads V’ state.
Conversion from one state to another takes place
according to the state diagram of Fig.5.
Fig.5 State diagram of PC2.
Output PC2produces positive or negative-going pulses
with variable width; they depend on the phase relationship
of R and V’. The average output voltage is a linear function
of the phase difference. Output PC2remains in the high
impedance OFF-state in the region in which PC1 operates.
The resultant phase characteristic is shown in Fig.6.
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January 1995 7
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Fig.6 Phase characteristic of PC2.
Strobe function
The strobe function is intended for applications requiring
extremely fast lock times. In normal operation the
additional strobe input (STB) can be connected to the
V-input and the circuit will function as described in the
previous sections.
In single, phase-locked-loop type frequency synthesizers,
the comparison frequency generally used is either the
nominal channel spacing or a sub-multiple. PC2 runs at
the higher frequency (a higher reference frequency must
also be used), whilst strobing takes place on the lower
frequency, thereby obtaining a decrease in lock time. In a
system using the Universal Divider HEF4751V, the output
OFS cycles on the lower frequency, the output OFF cycles
on the higher frequency.
Out-of-lock function
There are a number of situations in which the system goes
from the locked to the out-of-lock state (OL goes HIGH):
1. When V’ leads R, however out of the range of PC1.
2. When R leads V’.
3. When an R-pulse is missing.
4. When a V-pulse is missing.
5. When two successive STB-commands occur, the first
without corresponding V-signal.
Phase modulator
The phase modulator only uses one external capacitor,
C
B
at pin TCB. A negative-going transition at the V-input
causes CBto produce a positive-going linear ramp. When
the ramp has reached a value almost equal to the
modulation input voltage (at MOD), the ramp terminates,
CBdischarges and a start signal to the CA-ramp at TCA is
produced. A linear phase modulation is reached in this
way. If no modulation is required, the MOD-input must be
connected to a fixed voltage of a certain positive value up
to V
DD
. Care must be taken that the V’ pulse is never
smaller than the minimum value to ensure that the external
capacitor of PC1 (CA) can be discharged during that time.
Since the V’ pulse width is directly related to the TCB ramp
duration, there is a requirement for the minimum value of
this ramp duration.
Reference oscillator
The reference oscillator normally operates with an external
crystal as shown in Fig.2. The internal circuitry can be
used as a buffer amplifier in case an external reference
should be required.
Reference divider
The reference divider consists of a binary divider with a
programmable division ratio of 1 to 1024 and a prescaler
with selectable division ratios of 1, 2, 10 and 100,
according to the following tables:
Binary divider
Prescaler
N (A
0
TO A9) DIVISION RATIO
0 1024
0 ≤ N ≤ 1023 N
PROGRAMMING WORD
(NS
0
, NS1)
DIVISION RATIO
01
12
210
3 100
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January 1995 8
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
In this way suitable comparison frequencies can be
obtained from a range of crystal frequencies. The divider
can also be used as a ‘stand alone’ programmable divider
by connecting input TRA to VDD, which causes all internal
analogue currents to be switched off.
Biasing circuitry
The biasing circuitry uses an external current source or
resistor, which has to be connected between the TRA and
V
SS
pins. This circuitry supplies all analogue parts of the
circuit. Consequently the analogue properties of the
device, such as gain, charge currents, speed, power
dissipation, impedance levels etc., are mainly determined
by the value of the input current at TRA. The TRA input
must be decoupled to V
DD
, as shown in Fig.7. The value of
CDhas to be chosen such that the TRA input is ‘clean’, e.g.
10 nF at RA= 68 kΩ.
Fig.7 Decoupling of input TRA.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage V
DD
−0,5 to + 15 V
Voltage on any input V
I
−0,5 to VDD+ 0,5 V
D.C. current into any input or output ± I max. 10 mA
Power dissipation per package
for T
amb
= 0 to + 85 °CP
tot
max. 500 mW
Power dissipation per output
for T
amb
= 0 to 85 °C P max. 100 mW
Storage temperature T
stg
−65 to + 150 °C
Operating ambient temperature T
amb
−40 to + 85 °C
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January 1995 9
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
DC CHARACTERISTICS
at V
DD
= 10 V ± 5%; voltages are referenced to VSS= 0 V, unless otherwise specified; for definitions see note 1.
PARAMETER SYMBOL
T
amb
(°C
UNIT NOTES−40 + 25 + 85
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Quiescent device
current I
DD
−− 100 −− 100 −− 750 µA2
Input current; logic
inputs, MOD ± I
IN
−− 300 −− 300 −− 1000 nA 3
Output leakage current
at1⁄2V
DD
3,4
TCA, hold-state ± I
Z
−− 20 − 0,05 20 −− 60 nA
TCC, analogue
switch OFF ± I
Z
−− 20 − 0,05 20 −− 60 nA
PC
2
, high impedance
OFF-state ± I
Z
−− 50 −− 50 −− 500 nA
Logic input voltage
LOW V
IL
max. 0,3 VDD V
HIGH V
IH
max. 0,7 VDD V
Logic output voltage
LOW; at I
O
<1µAV
OL
−− 50 −− 50 −− 50 mV 3
HIGH V
OH
min. VDD− 50 mV mV 3
Logic output current
LOW; at VOL= 0,5 V 3
outputs OL, PC
2
,
OUT I
OL
5,5 −−4,6 −−3,6 −−mA
output XTAL I
OL
2,8 −−2,4 −−1,9 −−mA
Logic output current
HIGH;
at V
OH=VDD
− 0,5 V 3
outputs OL, PC
2
,OUT −I
OH
1,5 −−1,3 −−1,0 −−mA
output XTAL −I
OH
1,4 −−1,2 −−0,9 −−mA
Output TCC sink
current I
O
−− −−2,1 −− − −mA 3,4,5
Output TCC source
current −I
O
−− −−1,9 −− − −mA 3,4,6
Internal resistance
of TCC
output swing
≤ 200 mV
specified output range:
0,3 V
DD
to 0,7 V
DDRi
−− −−0,7 −− − −kΩ 3,4
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January 1995 10
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Output TCC voltage
with respect to
TCA input voltage ∆V − 0 −− 0 −− 0 −V 3,4,7
Output PC
1
sink
current I
O
−− −−1,1 −− − −mA 3,4,8
Output PC
1
source
current −I
O
−− −−1,0 −− − −mA 3,4,9
Internal resistance
of PC
1
output swing
≤ 200 mV
specified output range:
0,3 V
DD
to 0,7 V
DDRi
−− −−1,4 −− − −kΩ 3,4
Output PC
1
voltage
with respect to
TCC input voltage ∆V − 0 −− 0 −− 0 −V 3,4,10
EOR generation
V
EOR=VDD
− V
TCA
V
EOR
− 0,9 −− 0,7 −− 0,6 − V 3,4,11
Source current; HIGH
at V
OUT
=1⁄2VDD;
output in ramp mode 3,4
TCA I
O
−− −−13 −− − −mA
TCB I
O
−− −−2,5 −− − −mA
PARAMETER SYMBOL
T
amb
(°C
UNIT NOTES−40 + 25 + 85
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
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January 1995 11
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
AC CHARACTERISTICS
General note
The dynamic specifications are given for the circuit built-up with external components as given in Fig.8, under the
following conditions; for definitions see note 1; for definitions of times see Fig.19; V
DD
= 10 V ± 5%; T
amb
=25°C; input
transition times ≤ 20 ns; R
A
= 68 kΩ±30% (see also note 4); CA= 270 pF; CB= 150 pF; CC= 1 nF; CD= 10 nF; unless
otherwise specified.
SYMBOL MIN. TYP. MAX. UNIT CONDITIONS NOTES
Slew rate
TCA S
TCA
− 52 − V/µsR
A
= minimum 12
TCA S
TCA
− 28 − V/µsR
A
= maximum 12
TCB S
TCB
− 20 − V/µsR
A
= minimum 12
TCB S
TCB
− 10 − V/µsR
A
= maximum 12
Ramp linearity
TCA I
TCA
− 2 − %13
TCB I
TCB
− 2 − %13
Start of TCA-ramp delay t
CBCA
− 200 − ns
Delay of TCA-hold t
RCA
− 40 − ns
Delay of TCA-discharge t
VCA
− 60 − ns
Start of TCB-ramp delay t
VCB
− 60 − ns
TCB-ramp duration t
rCB
− 250 − ns V
MOD
=4V
t
rCB
− 350 − ns V
MOD
=6V
t
rCB
− 450 − ns V
MOD
=8V
Required TCB min.
ramp duration t
rCB
− 150 − ns 14
Pulse width
V : LOW t
PWVL
− 20 − ns
V : HIGH t
PWVH
− 20 − ns
R : LOW t
PWRL
− 20 − ns
R : HIGH t
PWRH
− 20 − ns
STB : LOW t
PWSL
− 20 − ns
STB : HIGH t
PWSH
− 20 − ns
Fall time
TCA t
fCA
− 50 − ns
TCB t
fCB
− 50 − ns
Prescaler input frequency f
PR
− 30 − MHz all division ratios
Binary divider frequency f
DIV
− 30 − MHz all division ratios
Crystal oscillator frequency f
OSC
− 10 − MHz
Average power supply current locked state
with speed-up 1 : 10 I
P
− 3,6 − mA 15
without speed-up I
P
− 3,2 − mA 16
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January 1995 12
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Notes
1. Definitions:
RA= external biasing resistor between pins TRA and VSS; 68 kΩ±30%.
CA= external timing capacitor for time/voltage converter, between pins TCA and VSS.
CB= external timing capacitor for phase modulator, between pins TCB and VSS.
CC= external hold capacitor between pins TCC and VSS.
CD= decoupling capacitor between pins TRA and VDD.
Logic inputs: V, R, STB, A0to A9, NS0, NS1, OSC.
Logic outputs: OL, PC2, XTAL, OUT.
Analogue signals: TCA, TCB, TCC, TRA, PC1, MOD.
2. TRA at VDD; TCA, TCB, TCC and MOD at VSS; logic inputs at VSSor VDD.
3. All logic inputs at VSSor VDD.
4. RAconnected; its value chosen such that I
TRA
= 100 µA.
5. The analogue switch is in the ON position (see Fig.9).
6. The analogue switch is in the ON position (see Fig.10).
7. See Fig.11.
This guarantees the d.c. voltage gain, combined with d.c.-offset.
Input condition: 0,3 VDD≤ V
TCA
≤ 0,7 VDD.
∆V=V
TCC−VTCA
.
8. See Fig.12.
9. See Fig.13.
10. See Fig.14.
This guarantees the d.c. voltage gain, combined with d.c.-offset.
Input condition: 0,3 VDD≤ V
TCC
≤ 0,7 VDD.
∆V=V
PC1−VTCC
.
11. Switching level at TCA, generating an EOR-signal, during increasing input voltage.
12. See Fig.15.
13. See Fig.16.
Definition of the ramp linearity at full swing.
14. The external components and modulation input voltage must be chosen such that this requirement will be fulfilled, to
ensure that CAis sufficiently discharged during that time.
15. See Fig.17.
Circuit connections for power supply current specification, with speed-up 1 : 10. V and R are in the range of PC1,
such that the output voltage at PC1is equal to 5 V.
f
OSC
= 5 MHz (external clock)
f
STB
= 12,5 kHz
fV= 125 kHz
16. See Fig.18.
Circuit connections for power supply current specification, without speed-up. V and R are in the range of PC1, such
that the output voltage at PC1is equal to 5 V.
f
OSC
= 5 MHz (external clock)
f
STB
= 12,5 kHz
fV= 12,5 kHz
Page 13
January 1995 13
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Fig.8 Test circuit for measuring a.c.
characteristics.
Fig.9 Equivalent circuit for note 5. Fig.10 Equivalent circuit for note 6.
Fig.11 Circuit for note 7. Fig.12 Equivalent circuit for PC1sink current.
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January 1995 14
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Fig.13 Equivalent circuit for PC1source current. Fig.14 Circuit for note 10.
Fig.15 Waveform at the output.
Fig.16 Definition of the ramp linearity at full swing.
∆V is the maximum deviation of the ramp waveform to the straight line, which joins the 30% VDDand
70% VDDpoints.
Linearity
∆V
1/2V
DD
--------------------- -
100× %.=
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January 1995 15
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Fig.17 Circuit for note 15.
Fig.18 Circuit for note 16.
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January 1995 16
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
Fig.19 Waveforms showing times in the locked state.
(1) Forbidden zone in the
locked state
for the positive edge of V and R and both edges of STB.
Page 17
January 1995 17
Philips Semiconductors Product specification
Frequency synthesizer
HEF4750V
LSI
APPLICATION INFORMATION
Fig.20 Application of HEF4750V as horizontal sync circuit with Phase-Locked Loop (PLL) and LC oscillator with
vari-cap control.
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