Datasheet HEF4023BU, HEF4023BT, HEF4023BPB, HEF4023BP, HEF4023BDB Datasheet (Philips)

DATA SH EET

Product specification
File under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF4023B
gates

Triple 3-input NAND gate

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

January 1995 2

Philips Semiconductors Product specification

Triple 3-input NAND gate

HEF4023B

gates

DESCRIPTION

The HEF4023B provides the positive triple 3-input NAND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.

Fig.1 Functional diagram.

HEF4023BP(N): 14-lead DIL; plastic

(SOT27-1)

HEF4023BD(F): 14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4023BT(D): 14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

Fig.2 Pinning diagram.

FAMILY DATA, IDDLIMITS category GATES

See Family Specifications

Fig.3 Logic diagram (one gate).

January 1995 3

Philips Semiconductors Product specification

Triple 3-input NAND gate

HEF4023B

gates

AC CHARACTERISTICS

V

SS

= 0 V; T

amb

=25°C; CL= 50 pF; input transition times ≤20 ns

V

DD

V

SYMBOL TYP. MAX.

TYPICAL EXTRAPOLATION

FORMULA

Propagation delays

In→ O

n

5 65 135 ns 38 ns + (0,55 ns/pF) C

L

HIGH to LOW 10 t

PHL

25 50 ns 14 ns + (0,23 ns/pF) C

L

15 15 30 ns 7 ns + (0,16 ns/pF) C

L

5 65 130 ns 38 ns + (0,55 ns/pF) C

L

LOW to HIGH 10 t

PLH

30 60 ns 19 ns + (0,23 ns/pF) C

L

15 25 45 ns 17 ns + (0,16 ns/pF) C

L

Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C

L

HIGH to LOW 10 t

THL

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

5 60 120 ns 10 ns + (1,0 ns/pF) C

L

LOW to HIGH 10 t

TLH

30 60 ns 9 ns + (0,42 ns/pF) C

L

15 20 40 ns 6 ns + (0,28 ns/pF) C

L

V

DD

V

TYPICAL FORMULA FOR P (µW)

Dynamic power 5 1200 f

i

+∑(foCL) × V

DD

2

where

dissipation per 10 5500 f

i

+∑(foCL) × V

DD

2

fi= input freq. (MHz)

package (P) 15 16 400 f

i

+∑(foCL) × V

DD

2

fo= output freq. (MHz)
C

L

= load capacitance (pF)

∑ (f

oCL

) = sum of outputs

V

DD

= supply voltage (V)