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HD74LV393A
Dual 4-bit Binary Counters
ADE-205-276 (Z)
1st Edition
April 1999
Description
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single
divide-by-256 counter.
The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and
each has an independent clear input. When clear is set high all four bits of each counter are set to a low
level. This enables count trucation and allows the implementation of divide-by-N counter configurations.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
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HD74LV393A
Function Table
Inputs
CLK CLR Output
XHL
H L No change
L L No change
↑ L No change
↓ L Count up
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Pin Arrangement
1CLK
1CLR
1QA
1QB
1QC
1QD
GND
V
1
2
3
4
5
6
7
(Top view)
14
13
12
11
10
9
8
CC
2CLK
2CLR
2QA
2QB
2QC
2QD
2
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HD74LV393A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
±70 mA
785 mW SOP
500 TSSOP
CC
3
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HD74LV393A
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV H or L
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
Logic Diagram
CLK
CLR
CK
QA
CK
Q
R
Q
R
QB
CK
QC
CK
Q
R
QD
Q
R
4
Page 5
Timing Diagram
CLK
CLR
QA
QB
QC
QD
HD74LV393A
5
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HD74LV393A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item Symbol VCC (V)* Min Typ Max Unit Test Conditions
Input voltage V
Output voltage V
Input current I
Quiescent
IH
V
IL
OH
V
OL
IN
I
CC
supply current
Output leakage
I
OFF
current
Input
C
IN
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2.0 1.5 — — V
2.3 to 2.7 VCC × 0.7 — —
3.0 to 3.6 VCC × 0.7 — —
4.5 to 5.5 VCC × 0.7 — —
2.0 — — 0.5
2.3 to 2.7 — — VCC × 0.3
3.0 to 3.6 — — VCC × 0.3
4.5 to 5.5 — — VCC × 0.3
Min to
VCC – 0.1 — — V IOL = –50 µA
Max
2.3 2.0 — — IOL = –2 mA
3.0 2.48 — — IOL = –6 mA
4.5 3.8 — — IOL = –12 mA
Min to
— — 0.1 V IOL = 50 µA
Max
2.3 — — 0.4 IOL = 2 mA
3.0 — — 0.44 IOL = 6 mA
4.5 — — 0.55 IOL = 12 mA
0 to 5.5 — — ±1 µAVIN = 5.5 V or GND
5.5 — — 20 µAVIN = VCC or GND, IO = 0
0——5 µAVI, or VO = 0 V to 5.5 V
3.3 — 1.7 — pF VI = VCC or GND
6
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Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay time
Setup time t
Pulse
width
fmax 50 90 — 40 — MHz CL = 15 pF
30 60 — 25 — CL = 50 pF
t
PLH/./tPHL
— 11.8 17.7 1.0 20.5 ns CL = 15 pF CLK Q
— 15.1 21.3 1.0 24.5 CL = 50 pF
— 13.4 20.3 1.0 23.5 CL = 15 pF Q
— 16.7 23.9 1.0 27.5 CL = 50 pF
— 14.9 22.5 1.0 26.0 CL = 15 pF Q
— 18.2 26.1 1.0 30.0 CL = 50 pF
— 16.2 24.2 1.0 28.0 CL = 15 pF Q
— 19.5 27.8 1.0 32.0 CL = 50 pF
t
PHL
— 10.8 14.8 1.0 17.0 CL = 15 pF CLR Q
— 14.2 17.4 1.0 20.0 CL = 50 pF
su
t
w
6.0 — — 6.0 — ns CLR L before CLK ↓
5.0 — — 5.0 — ns CLR H
5.0 — — 5.0 — CLK H or L
HD74LV393A
FROM
(Input)
TO
(Output)
A
B
C
D
n
7
Page 8
HD74LV393A
Switching Characteristics (cont)
• VCC = 3.3 ± 0.3 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay time
Setup time t
Pulse
width
fmax 75 120 — 65 — MHz CL = 15 pF
45 65 — 35 — CL = 50 pF
t
PLH/./tPHL
— 8.6 13.2 1.0 15.5 ns CL = 15 pF CLK Q
— 11.1 16.7 1.0 19.0 CL = 50 pF
— 10.2 15.8 1.0 18.5 CL = 15 pF Q
— 12.7 19.3 1.0 22.0 CL = 50 pF
— 11.7 18.0 1.0 21.0 CL = 15 pF Q
— 14.2 21.5 1.0 24.5 CL = 50 pF
— 13.0 19.7 1.0 23.0 CL = 15 pF Q
— 15.5 23.2 1.0 26.5 CL = 50 pF
t
PHL
— 7.9 12.3 1.0 14.5 CL = 15 pF CLR Q
— 10.4 15.8 1.0 18.0 CL = 50 pF
su
t
w
5.0 — — 5.0 — ns CLR L before CLK ↓
5.0 — — 5.0 — ns CLR H
5.0 — — 5.0 — CLK H or L
FROM
(Input)
TO
(Output)
A
B
C
D
n
8
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Switching Characteristics (cont)
• VCC = 5.0 ± 0.5 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay time
Setup time t
Pulse
width
fmax 125 170 — 105 — MHz CL = 15 pF
85 115 — 75 — CL = 50 pF
t
PLH/./tPHL
— 5.8 8.5 1.0 10.0 ns CL = 15 pF CLK Q
— 7.3 10.5 1.0 12.0 CL = 50 pF
— 6.8 9.8 1.0 11.5 CL = 15 pF Q
— 8.3 11.8 1.0 13.5 CL = 50 pF
— 7.7 11.2 1.0 13.0 CL = 15 pF Q
— 9.2 13.2 1.0 15.0 CL = 50 pF
— 8.5 12.5 1.0 14.5 CL = 15 pF Q
— 10.0 14.5 1.0 16.5 CL = 50 pF
t
PHL
— 5.4 8.1 1.0 9.5 CL = 15 pF CLR Q
— 6.9 10.1 1.0 11.5 CL = 50 pF
su
t
w
4.0 — — 4.0 — ns CLR L before CLK ↓
5.0 — — 5.0 — ns CLR H
5.0 — — 5.0 — CLK H or L
HD74LV393A
FROM
(Input)
TO
(Output)
A
B
C
D
n
9
Page 10
HD74LV393A
Operating Characteristics
• CL = 50 pF
Item Symbol V
Power
C
PD
dissipation
capacitance
Test Circuit
(V) Min Typ Max Unit Test Conditions
CC
3.3 — 12.0 — pF f = 10 MHz
5.0 — 15.0 —
Ta = 25°C
Measurement point
*
C
L
Note: C includes the probe and jig capacitance.
L
10
Page 11
•
Waveforms – 1
CLR
CLK
Q
n
•
Waveforms – 2
10 %
t
t
r
r
90 %
50 % V
t
f
CC
t
w
10 %
t
f
90 % 90 %
50 % V
CC
10 %
t
su
t
t
w
PLH
50 % V
t
r
50 % V
CC
CC
t
w
50 % V
t
PHL
CC
HD74LV393A
V
CC
0 V
V
CC
0 V
V
OH
V
OL
t
f
V
CC
0 V
V
V
CC
OH
OL
Q
n
Q
n
CLR CLK
10 %
Q
n
Notes:
50 % V
CC
t
PHL
50 % V
1. Input waveform: PRR ≤ 10 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns
90 %
2. The output are measured one at a time with one transition per measurement.
90 %
50 % V
CC
10 %
t
50 % V
t
50 % V
rf
PHL
PLH
CC
CC
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
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Page 12
HD74LV393A
Package Dimensions
14
1
1.27
10.06
10.5 Max
1.42 Max
8
5.5
7
+ 0.20
7.80
– 0.30
1.15
2.20 Max
0.22 ± 0.05
0.20 ± 0.04
0° – 8°
0.70 ± 0.20
0.42 ± 0.08
0.40 ± 0.06
Dimension including the plating thickness
Base material dimension
0.12
0.10 ± 0.10
0.15
M
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-14DA
—
Conforms
0.23 g
12
Page 13
14
HD74LV393A
Unit: mm
8.65
9.05 Max
8
1
0.635 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
7
+ 0.11
0.25
3.95
– 0.04
0.14
0.15
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
+ 0.67
0.60
– 0.20
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
(reference value)
FP-14DN
Conforms
Conforms
0.13 g
13
Page 14
HD74LV393A
0.22
0.20 ± 0.06
5.00
5.30 Max
14 8
4.40
17
0.65
+0.08
–0.07
0.13
M
0.83 Max
1.0
6.40 ± 0.20
0.10
1.10 Max
Dimension including the plating thickness
Base material dimension
0.17 ± 0.05
0.15 ± 0.04
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
0.50 ± 0.10
TTP-14D
—
—
0.05 g
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Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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