Page 1
HD74LV175A
Quad. D-type Flip-Flops with Clear
ADE-205-270 (Z)
1st Edition
April 1999
Description
Information at the D inputs of the HD74LV175A is transferred to the Q and Q outputs on the positive going
edge of the clock pulse. Both true and complement outputs from each flip-flop are externally available.
All four flip-flops are controlled by a common clock and common clear. Clearing is accomplished by a
negative pulse at the clear input. All four Q outputs are cleared to a logic low level and all four Q outputs
to a logic high level. Low-voltage and high-speed operation is suitable for battery-powered products (e.g.,
notebook computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Function Table
Inputs Outputs
CLR CLK D Q Q
LX XL H
H ↑ HH L
H ↑ LL H
H ↓ X no change no change
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Page 2
HD74LV175A
Pin Arrangement
CLR
V
1
16
CC
1Q
1Q
1D
2D
2Q
2Q
GND
2
3
4
5
6
7
8
(Top view)
15
14
13
12
11
10
4Q
4Q
4D
3D
3Q
3Q
9
CLK
2
Page 3
HD74LV175A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
±50 mA
785 mW SOP
500 TSSOP
CC
3
Page 4
HD74LV175A
Q
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV H or L
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
Logic Diagram
CLR
CLK
1D
1
9
3
To Three Other Channels
1D
R
C1
2
1Q
3
1
4
Page 5
HD74LV175A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item Symbol VCC (V)* Min Typ Max Unit Test Conditions
Input voltage V
Output voltage V
Input current I
Quiescent
IH
V
IL
OH
V
OL
IN
I
CC
supply current
Output leakage
I
OFF
current
Input
C
IN
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2.0 1.5 — — V
2.3 to 2.7 VCC × 0.7 — —
3.0 to 3.6 VCC × 0.7 — —
4.5 to 5.5 VCC × 0.7 — —
2.0 — — 0.5
2.3 to 2.7 — — VCC × 0.3
3.0 to 3.6 — — VCC × 0.3
4.5 to 5.5 — — VCC × 0.3
Min to
VCC – 0.1 — — V IOH = –50 µA
Max
2.3 2.0 — — IOH = –2 mA
3.0 2.48 — — IOH = –6 mA
4.5 3.8 — — IOH = –12 mA
Min to
— — 0.1 IOL = 50 µA
Max
2.3 — — 0.4 IOL = 2 mA
3.0 — — 0.44 IOL = 6 mA
4.5 — — 0.55 IOL = 12 mA
0 to 5.5 — — ±1 µAVI = 5.5 V or GND
5.5 — — 20 µAVI = VCC or GND, IO = 0
0——5 µAVI or VO = 0 V to 5.5 V
3.3 — 1.4 — pF VI = VCC or GND
5
Page 6
HD74LV175A
Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay
time
Setup
time
fmax 50 105 — 45 — MHz CL = 15 pF
40 80 — 35 — CL = 50 pF
t
PLH
/ t
— 9.3 18.8 1.0 22.0 ns CL = 15 pF CLK Q, Q
PHL
— 12.0 23.3 1.0 27.0 CL = 50 pF
t
PHL
— 7.9 16.6 1.0 20.0 CL = 15 pF CLR
— 10.4 21.6 1.0 25.5 CL = 50 pF
t
SU
7.0 — — 7.5 — ns Data before CLK↑
FROM
(Input)TO(Output)
Hold
time
Pulse
width
7.0 — — 7.5 — CLR inactive before
CLK↑
t
h
t
W
0.5 — — 1.0 — ns Data after CLK↑
6.0 — — 6.0 — ns CLR L
6.5 — — 7.0 — CLK H or L
6
Page 7
Switching Characteristics (cont)
VCC = 3.3 ± 0.3 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay
time
Setup
time
fmax 90 155 — 75 — MHz CL = 15 pF
50 120 — 45 — CL = 50 pF
t
PLH
/ t
— 6.5 11.5 1.0 13.5 ns CL = 15 pF CLK Q, Q
PHL
— 8.4 15.0 1.0 17.0 CL = 50 pF
t
PLH
/ t
— 5.5 10.1 1.0 12.0 CL = 15 pF CLR
PHL
— 7.4 13.6 1.0 15.5 CL = 50 pF
t
SU
5.0 — — 5.0 — ns Data before CLK↑
HD74LV175A
FROM
(Input)TO(Output)
Hold
time
Pulse
width
5.0 — — 5.0 — CLR inactive before
CLK↑
t
h
t
W
1.0 — — 1.0 — ns Data after CLK↑
5.0 — — 5.0 — ns CLR L
5.0 — — 5.0 — CLK H or L
7
Page 8
HD74LV175A
Switching Characteristics (cont)
VCC = 5.0 ± 0.5 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay
time
Setup
time
fmax 150 215 — 125 — MHz CL = 15 pF
85 165 — 75 — CL = 50 pF
t
PLH
/ t
— 4.6 7.3 1.0 8.5 ns CL = 15 pF CLK Q, Q
PHL
— 6.0 9.3 1.0 10.5 CL = 50 pF
t
PLH
/ t
— 3.7 6.4 1.0 7.5 CL = 15 pF CLR
PHL
— 5.3 8.4 1.0 9.5 CL = 50 pF
t
SU
4.0 — — 4.0 — ns Data before CLK↑
FROM
(Input)TO(Output)
Hold
time
Pulse
width
5.0 — — 5.0 — CLR inactive before
CLK↑
t
h
t
W
1.0 — — 1.0 — ns Data after CLK↑
5.0 — — 5.0 — ns CLR L
5.0 — — 5.0 — CLK H or L
8
Page 9
HD74LV175A
Output-skew Characteristics
Ta = 25°C Ta = –40 to 85°C
Item Symbol V
Output skew t
sk (O)
Note: Skew between any outputs of the same package switching in the same direction. This parameter is
warranted but not production tested.
Operating Characteristics
• CL = 50 pF
Item Symbol V
Power
dissipation
capacitance
C
PD
= (V) Min Typ Max Min Max Unit
CC
2.3 to 2.7 — — 2.0 — 2.0 ns
3.0 to 3.6 — — 1.5 — 1.5
4.5 to 5.5 — — 1.0 — 1.0
Ta = 25°C
= (V) Min Typ Max Unit Test Conditions
CC
3.3 — 13.6 — pF f = 10 MHz
5.0 — 14.5 —
Noise Characteristics
• CL = 50 pF
Item Symbol V
Quiet output,
maximum
dynamic V
Quiet output,
minimum
dynamic V
Quiet output,
minimum
dynamic V
High-level
dynamic
input voltage
Low-level
dynamic
input voltage
V
OL (P)
OL
V
OL (V)
OL
V
OH (V)
OH
V
IH (D)
V
IL (D)
Ta = 25°C
= (V) Min Typ Max Unit Test Conditions
CC
3.3 — 0.3 0.8 V
3.3 — –0.3 –0.8
3.3 — 3.0 —
3.3 2.31 — — V
3.3 — — 0.99
9
Page 10
HD74LV175A
Test Circuit
Measurement point
*
C
L
Note: C includes the probe and jig capacitance.
L
10
Page 11
HD74LV175A
•
Waveform-1
Timing input
Data input
Input
•
Waveform-2
Input
10 %
t
r
50 % V
10 %
t
50 % V
50 % V
90 %
t
PLH
su
CC
CC
CC
t
r
50 % V
50 % V
90 %
t
w
90 %
CC
t
h
50 % V
50 % V
t
f
CC
50 % V
CC
CC
10 %
90 %
t
PHL
CC
t
f
V
CC
10 %
0 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
In phase output
Out of phase output
Notes:
1. I
2. The output is measured one at a time with one transition per measurement.
t
PHL
nput waveform: PRR ≤ 1
50 % V
CC
50 % V
CC
MHz, Zo = 50 Ω,
50 % V
t
PLH
50 % V
tr ≤ 3 ns, tf ≤ 3 ns
CC
CC
V
OH
V
OL
V
OH
V
OL
11
Page 12
HD74LV175A
Package Dimensions
16
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
0.42 ± 0.08
± 0.06
0.40
Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.22 ± 0.05
0.20 ± 0.04
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
+ 0.20
– 0.30
1.15
0
° – 8°
FP-16DA
—
Conforms
0.24 g
12
Page 13
16
HD74LV175A
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
+ 0.67
0.60
– 0.20
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
13
Page 14
HD74LV175A
0.22
0.20 ± 0.06
5.0
5.3 Max
16 9
4.40
18
0.65
+ 0.08
– 0.07
0.13
0.65 Max
1.0
M
6.40 ± 0.20
0.10
1.10 Max
Dimension including the plating thickness
Base material dimension
0.17 ± 0.05
0.15 ± 0.04
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
0.50 ± 0.10
TTP-16DA
—
—
0.05 g
14
Page 15
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL NorthAmerica : http:semiconductor.hitachi.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Europe : http://www.hitachi-eu.com/hel/ecg
Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan : http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Europe GmbH
Electronic components Group
Dornacher Stra§e 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Loading...