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HD74LV166A
Parallel-Load 8-bit Shift Register
ADE-205-268 (Z)
1st Edition
March 1999
Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the
register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded
asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge
of either clock inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
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HD74LV166A
Function Table
Inputs Internal outputs Output
CLR SH/LD CLK INH CLK SER A ... H QA QB QH
LXXXXXLL L
HXLLXXQA0Q
B0
HLL ↑ X a ... h a b h
HHL ↑ HXHQAnQ
HHL ↑ LXLQAnQ
HXH↑ XXQA0Q
B0
Note: H: High level
L: Low level
↑: Low to high transition
X: Immaterial
a ... h: Parallel data
... QH0: Outputs remain unchanged.
Q
A0
Q
... QGn: Data shifted from the previous stage on a positive edge at the clock input.
An
Q
H0
Gn
Gn
Q
H0
Pin Arrangement
SER
CLK INH
CLK
GND
V
1
2
A
3
B
4
C
5
D
6
7
8
16
15
14
13
12
11
10
9
CC
SH/LD
H
QH
G
F
E
CLR
(Top view)
2
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HD74LV166A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
±50 mA
785 mW SOP
500 TSSOP
CC
3
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HD74LV166A
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV H or L
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
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Logic Diagram
HD74LV166A
ACBDEFCLR SH/LDGH
SER
RCPS
CDQ
RCPS
D
C
CLK CLK INH
Q
QH
5
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HD74LV166A
Timing Diagram
CLK
CLK INH
CLR
SER
SH/LD
Parallel
Inputs
Output Q
A
B
C
D
E
F
G
H
H
Clear Load
Serial shift Serial shiftInhibit
H
L
H
L
H
L
H
H
HH H
H
HLLLL
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HD74LV166A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item Symbol VCC (V)* Min Typ Max Unit Test Conditions
Input voltage V
Output voltage V
Input current I
Quiescent
IH
V
IL
OH
V
OL
IN
I
CC
supply current
Output leakage
I
OFF
current
Input
C
IN
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2.0 1.5 — — V
2.3 to 2.7 VCC × 0.7 — —
3.0 to 3.6 VCC × 0.7 — —
4.5 to 5.5 VCC × 0.7 — —
2.0 — — 0.5
2.3 to 2.7 — — VCC × 0.3
3.0 to 3.6 — — VCC × 0.3
4.5 to 5.5 — — VCC × 0.3
Min to
VCC – 0.1 — — V IOL = –50 µA
Max
2.3 2.0 — — IOL = –2 mA
3.0 2.48 — — IOL = –6 mA
4.5 3.8 — — IOL = –12 mA
Min to
— — 0.1 IOL = 50 µA
Max
2.3 — — 0.4 IOL = 2 mA
3.0 — — 0.44 IOL = 6 mA
4.5 — — 0.55 IOL = 12 mA
0 to 5.5 — — ±1 µAVI = 5.5 V or GND
5.5 — — 20 µAVI = VCC or GND, IO = 0
0——5 µAVI or VO = 0 V to 5.5 V
3.3 — 1.7 — pF VI = VCC or GND
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HD74LV166A
Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
fmax 50 80 — 45 — MHz CL = 15 pF
40 65 — 35 — CL = 50 pF
t
PLH/tPHL
— 12.2 19.8 1.0 22.0 ns CL = 15 pF CLK Q
— 15.3 23.3 1.0 26.0 CL = 50 pF
t
PHL
— 10.8 16.0 1.0 18.0 CL = 15 pF CLR
— 14.2 19.5 1.0 22.0 CL = 50 pF
su
7.0 — — 7.0 — ns CLK INH before CLK ↑
6.5 — — 8.5 — Data before CLK ↑
7.0 — — 8.5 — ns SH/LD high before CLK ↑
8.5 — — 9.5 — SER before CLK ↑
h
–0.5 — — 0.0 — ns PAR data after SH/LD ↑
–0.5 — — 0.0 — SER data after CLK ↑
–0.5 — — 0.0 — SH/LD high after CLK ↑
t
w
8.0 — — 9.0 — ns CLR low
8.5 — — 9.0 — CLK H or L
Test
Conditions
FROM
(Input)
TO
(Output)
H
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Switching Characteristics (cont)
• VCC = 3.3 ± 0.3 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
fmax 65 115 — 55 — MHz CL = 15 pF
60 90 — 50 — CL = 50 pF
t
PLH/tPHL
— 8.6 15.4 1.0 18.0 ns CL = 15 pF CLK Q
— 10.9 18.9 1.0 21.5 CL = 50 pF
t
PHL
— 7.9 12.5 1.0 15.0 CL = 15 pF CLR
— 10.4 16.3 1.0 18.5 CL = 50 pF
su
5.0 — — 5.0 — ns CLK INH before CLK ↑
5.0 — — 6.0 — Data before CLK ↑
5.0 — — 6.0 — ns SH/LD high before CLK ↑
5.0 — — 6.0 — SER before CLK ↑
h
0.0 — — 0.0 — ns PAR data after SH/LD ↑
0.0 — — 0.0 — SER data after CLK ↑
0.0 — — 0.0 — SH/LD high after CLK ↑
t
w
6.0 — — 7.0 — ns CLR low
6.0 — — 7.0 — CLK H or L
Test
Conditions
HD74LV166A
FROM
(Input)
TO
(Output)
H
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HD74LV166A
Switching Characteristics (cont)
• VCC = 5.0 ± 0.5 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
fmax 110 165 — 90 — MHz CL = 15 pF
95 125 — 85 — CL = 50 pF
t
PLH/tPHL
— 6.0 9.9 1.0 11.5 ns CL = 15 pF CLK Q
— 7.7 11.9 1.0 13.5 CL = 50 pF
t
PHL
— 5.4 8.6 1.0 10.0 CL = 15 pF CLR
— 6.9 10.6 1.0 12.0 CL = 50 pF
su
3.5 — — 3.5 — ns CLK INH before CLK ↑
4.5 — — 4.5 — Data before CLK ↑
4.0 — — 4.0 — ns SH/LD high before CLK ↑
4.0 — — 4.0 — SER before CLK ↑
h
1.0 — — 1.0 — ns PAR data after SH/LD ↑
1.0 — — 1.0 — SER data after CLK ↑
1.0 — — 1.0 — SH/LD high after CLK ↑
t
w
5.0 — — 5.0 — ns CLR low
4.0 — — 4.0 — CLK H or L
Test
Conditions
FROM
(Input)
TO
(Output)
H
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Operating Characteristics
• CL = 50 pF
Item Symbol V
Power
C
PD
dissipation
capacitance
(V) Min Typ Max Unit Test Conditions
CC
3.3 — 36.1 — pF f = 10 MHz
5.0 — 37.5 —
Test Circuit
Ta = 25°C
Measurement point
*
C
L
HD74LV166A
Note: C includes the probe and jig capacitance.
L
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HD74LV166A
Waveform
CLR
CLK
Data
Output Q
H
50%V
50%V
CC
tW
50%V
50%V
CC
CC
tW
50%V
CC
tPHL tPHL
50%V
CC
CC
tn+1 tn+1
tn tn
50%V
CC
th
tsu tsu
50%V
CC
50%V
CC
50%V
CC
50%V
th
tPHL
50%V
CC
50%V
CC
CC
V
CC
0 V
V
CC
0 V
V
CC
0 V
VOH
VOL
1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns
Notes:
rf
2. The output are measured one at a time with one transition per measurement.
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Package Dimensions
16
HD74LV166A
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
0.42 ± 0.08
0.40 ± 0.06
Dimension including the plating thickness
Base material dimension
8
0.10 ± 0.10
0.15
0.12
2.20 Max
M
7.80
0.22 ± 0.05
0.20 ± 0.04
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
+ 0.20
– 0.30
1.15
0° – 8°
FP-16DA
—
Conforms
0.24 g
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HD74LV166A
16
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
0.60
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
+ 0.67
– 0.20
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
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16 9
18
+ 0.08
0.22
– 0.07
0.20 ± 0.06
5.0
5.3 Max
0.65 Max
0.65
0.13
HD74LV166A
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
Dimension including the plating thickness
Base material dimension
+0.03
–0.04
0.07
0.17 ± 0.05
0.15 ± 0.04
0° – 8°
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
0.50 ± 0.10
TTP-16DA
—
—
0.05 g
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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