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HD74LV165A
Parallel-Load 8-bit Shift Register
ADE-205-267 (Z)
1st Edition
March 1999
Description
The HD74LV165A is 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to
each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a
complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and high enables the other clock input.
Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the
Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register
independent of the state of the clock.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
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HD74LV165A
Function Table
Inputs Internal Outputs Output
SH/LD CLK INH CLK SER A ... H QA QB QH
L X X X a ... h a b h
HL ↑ HX HQAnQ
HL ↑ LXLQAnQ
HHXXXQA0Q
HXHXXQA0Q
B0
B0
H ↑ LHXHQAnQ
H ↑ LLXLQAnQ
Note: H: High level
L: Low level
↑: Low to high transition
X: Immaterial
a ... h: Parallel data
Q
... QH0: Outputs remain unchanged.
A0
Q
... QGn: Data shifted from the previous stage on a positive edge at the clock input.
An
Gn
Gn
Q
H0
Q
H0
Gn
Gn
Pin Arrangement
SH/LD
CLK
Q
GND
V
1
2
3
E
4
F
5
G
6
H
7
H
8
16
15
14
13
12
11
10
9
CC
CLK INH
D
C
B
A
SER
Q
H
(Top view)
2
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HD74LV165A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
±50 mA
785 mW SOP
500 TSSOP
CC
3
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HD74LV165A
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV H or L
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
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Logic Diagram
HD74LV165A
1
SH/LD
15
CLK INH
2
CLK
10
SER
Timing Diagram
CLK INH
SH/LD
CLK
SER
A
11
B
12
S
C1
1D
R
C
13
S
C1
1D
R
D
14
S
C1
1D
R
E
3
S
C1
1D
R
F
4
S
C1
1D
R
G
5
S
C1
1D
R
H
6
S
C1
1D
R
S
9
C1
1D
R
Q
H
7
Q
H
L
A
H
Data
Inputs
B
C
D
E
F
G
H
Q
H
Q
H
L
H
L
H
L
H
H
LLL
HHHH
H
HHH
LLLLL
Inhibit Serial Shift
Load
5
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HD74LV165A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item Symbol VCC (V)* Min Typ Max Unit Test Conditions
Input voltage V
Output voltage V
Input current I
Quiescent
IH
V
IL
OH
V
OL
IN
I
CC
supply current
Output leakage
I
OFF
current
Input
C
IN
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2.0 1.5 — — V
2.3 to 2.7 VCC × 0.7 — —
3.0 to 3.6 VCC × 0.7 — —
4.5 to 5.5 VCC × 0.7 — —
2.0 — — 0.5
2.3 to 2.7 — — VCC × 0.3
3.0 to 3.6 — — VCC × 0.3
4.5 to 5.5 — — VCC × 0.3
Min to
VCC – 0.1 — — V IOL = –50 µA
Max
2.3 2.0 — — IOL = –2 mA
3.0 2.48 — — IOL = –6 mA
4.5 3.8 — — IOL = –12 mA
Min to
— — 0.1 IOL = 50 µA
Max
2.3 — — 0.4 IOL = 2 mA
3.0 — — 0.44 IOL = 6 mA
4.5 — — 0.55 IOL = 12 mA
0 to 5.5 — — ±1 µAVI = 5.5 V or GND
5.5 — — 20 µAVI = VCC or GND, IO = 0
0——5 µAVI or VO = 0 V to 5.5 V
3.3 — 1.7 — pF VI = VCC or GND
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Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
fmax 50 80 — 45 — MHz CL = 15 pF
40 65 — 35 — CL = 50 pF
t
PLH/tPHL
— 13.1 21.5 1.0 23.5 ns CL = 15 pF SH/LD Q
— 16.1 25.1 1.0 28.0 CL = 50 pF
— 12.2 19.8 1.0 22.0 CL = 15 pF CLK
— 15.3 23.3 1.0 26.0 CL = 50 pF
— 12.9 21.7 1.0 24.0 CL = 15 pF H
— 15.9 25.3 1.0 28.0 CL = 50 pF
su
7.0 — — 7.0 — ns CLK INH before CLK ↑
11.5 — — 12.0 — data before SH/LD ↑
7.0 — — 8.5 — ns SH/LD high before CLK ↑
8.5 — — 9.5 — SER before CLK ↑
h
0.0 — — 0.5 — ns PAR data after SH/LD ↑
–1.0 — — 0.0 — SER data after CLK ↑
0.0 — — 0.0 — SH/LD high atfer CLK ↑
t
w
11.0 — — 13.0 — ns SH/LD low
8.5 — — 9.0 — CLK H or L
Test
Conditions
HD74LV165A
FROM
(Input)
TO
(Output)
or Q
H
H
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HD74LV165A
Switching Characteristics (cont)
• VCC = 3.3 ± 0.3 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
fmax 65 115 — 55 — MHz CL = 15 pF
60 90 — 50 — CL = 50 pF
t
PLH/tPHL
— 9.1 15.8 1.0 18.5 ns CL = 15 pF SH/LD Q
— 11.3 19.3 1.0 22.0 CL = 50 pF
— 8.6 15.4 1.0 18.0 CL = 15 pF CLK
— 10.9 18.9 1.0 21.5 CL = 50 pF
— 8.9 14.1 1.0 16.5 CL = 15 pF H
— 11.1 17.6 1.0 20.0 CL = 50 pF
su
5.0 — — 5.0 — ns CLK INH before CLK ↑
7.5 — — 8.5 — data before SH/LD ↑
5.0 — — 6.0 — ns SH/LD high before CLK ↑
5.0 — — 6.0 — SER before CLK ↑
h
0.5 — — 0.5 — ns PAR data after SH/LD ↑
0.0 — — 0.0 — SER data after CLK ↑
0.0 — — 0.0 — SH/LD high atfer CLK ↑
t
w
7.5 — — 9.0 — ns SH/LD low
6.0 — — 7.0 — CLK H or L
Test
Conditions
FROM
(Input)
TO
(Output)
or Q
H
H
8
Page 9
Switching Characteristics (cont)
• VCC = 5.0 ± 0.5 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
fmax 110 165 — 90 — MHz CL = 15 pF
95 125 — 85 — CL = 50 pF
t
PLH/tPHL
— 6.0 9.9 1.0 11.5 ns CL = 15 pF SH/LD Q
— 7.7 11.9 1.0 13.5 CL = 50 pF
— 6.0 9.9 1.0 11.5 CL = 15 pF CLK
— 7.7 11.9 1.0 13.5 CL = 50 pF
— 6.0 9.0 1.0 10.5 CL = 15 pF H
— 7.6 11.0 1.0 12.5 CL = 50 pF
su
3.5 — — 3.5 — ns CLK INH before CLK ↑
5.0 — — 5.0 — data before SH/LD ↑
4.0 — — 4.0 — ns SH/LD high before CLK ↑
4.0 — — 4.0 — SER before CLK ↑
h
1.0 — — 1.0 — ns PAR data after SH/LD ↑
0.5 — — 0.5 — SER data after CLK ↑
0.5 — — 0.5 — SH/LD high atfer CLK ↑
t
w
5.0 — — 6.0 — ns SH/LD low
4.0 — — 4.0 — CLK H or L
Test
Conditions
HD74LV165A
FROM
(Input)
TO
(Output)
or Q
H
H
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Page 10
HD74LV165A
Operating Characteristics
• CL = 50 pF
Item Symbol V
Power
C
PD
dissipation
capacitance
Test Circuit
(V) Min Typ Max Unit Test Conditions
CC
3.3 — 36.1 — pF f = 10 MHz
5.0 — 37.5 —
Ta = 25°C
Measurement point
*
C
L
Note: C includes the probe and jig capacitance.
L
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Waveform
Waveform – 1
CK INH
QH, QH
Sereial mode
SER
CK or
50% V
CC
t
su
tw(L) tw(H)
t
h
50% V
t
PLH
CC
50% V
, t
CC
PHL
50% V
t
su
CC
HD74LV165A
V
GND
t
h
V
50% V
CC
GND
V
50% V
CC
V
t
, t
PLH
PHL
CC
CC
OH
OL
Waveform – 2
Parallel mode
SH/LD
QH, QH
50% V
t
PLH
CC
tw(L)
50% V
CC
t
PHL
V
CC
GND
V
OH
V
OL
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HD74LV165A
Waveform – 3
Sereial mode
CK INH
CK
Waveform – 4
Parallel mode
Input H
50% V
tsu
t
r
50% V
10%
90%
CC
50% V
CC
CC
V
CC
GND
V
CC
GND
tf
V
CC
GND
QH
QH
t
PLH
t
PHL
50% V
50% V
CC
CC
t
PHL
t
PLH
50% V
50% V
CC
CC
V
OH
V
OL
V
OH
V
OL
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Waveform – 5
Parallel mode
Waveform – 6
sereial mode
SH/LD
Input
A to H
SH/LD
50% V
t
su
50% V
CC
CC
t
h
50% V
CC
HD74LV165A
V
CC
GND
V
CC
GND
V
CC
t
su
CK or
CK INH
1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns
Notes:
2. The output are measured one at a time with one transition per measurement.
50% V
CC
rf
GND
V
CC
GND
13
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HD74LV165A
Package Dimensions
16
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
0.42 ± 0.08
± 0.06
0.40
Dimension including the plating thickness
Base material dimension
8
0.12
2.20 Max
0.10 ± 0.10
0.15
M
7.80
0.22 ± 0.05
0.20 ± 0.04
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
+ 0.20
– 0.30
1.15
0
° – 8°
FP-16DA
—
Conforms
0.24 g
14
Page 15
16
HD74LV165A
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
0.60
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
+ 0.67
– 0.20
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
15
Page 16
HD74LV165A
0.22
0.20 ± 0.06
5.0
5.3 Max
16 9
4.40
18
0.65
+ 0.08
– 0.07
0.13
0.65 Max
1.0
M
6.40 ± 0.20
0.10
1.10 Max
Dimension including the plating thickness
Base material dimension
0.17 ± 0.05
0.15 ± 0.04
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
0.50 ± 0.10
TTP-16DA
—
—
0.05 g
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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